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ECEN 2350 - Digital Logic

Catalog Data ECEN 2350 (3). Digital Logic. Covers the design and applications of digital logic circuits, including combinational and sequential logic circuits.
Credits and Design 3 credit hours. Required core course.
Prerequisite(s) ECEN 1030, C Programming for EE/ECE. (or CSCI 1300)
Corequisite(s) None.
Instructor(s) Andrew Pleszkun, Fabio Somenzi.
Textbook Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, 2nd Edition, McGraw-Hill, 2008, ISBN 978-0-07-338033-9.
  
Course Objectives For students to:
  1. To understand how logic circuits are used to solve engineering problems.
  2. To understand how logic circuits are analyzed, designed, verified, and tested.
  3. To understand the relationship between the logic and the electrical level.
Learning Outcomes After taking this course students will be able to recognize and use the following concepts, ideas, and/or tools:
  1. Logic level models, including Boolean algebra, finite state machines, and hardware description languages.
  2. Logic gates, memory, including CMOS gates, flip-flops, arrays, and programmable logic.
  3. Design tools, both manual and computerized, for design and test of logic circuits.
  4. Design criteria, including area, speed, power consumption, and testability.
Student Outcomes
Addressed
3a 3b 3c 3d 3e 3f 3g1 3g2 3h 3i 3j 3k
Math
/Sci		 Exper-
iments		 Design Teams Engr
Problems		 Respon-
sibility		 Oral Written Engr Solns
Impact		 LL
Learning		 Contem-
porary		 Tools
H   L   M             L
Topics Covered
  1. Boolean algebra
  2. Combinational logic gates
  3. CMOS technology and programmable logic
  4. The Verilog Hardware Description Language (VHDL)
  5. Combinational circuit synthesis and optimization
  6. Digital storage elements
  7. Synchronous design methodology
  8. Finite state machines
  9. Sequential circuits synthesis and optimization
  10. Counters
  11. Dynamic logic, buses and memory arrays
  12. Testing and testability of logic circuits

Last revised: 05-21-11, PM, ARP.