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ECEN 4633 - Hybrid Embedded Systems

Catalog Data ECEN 4633 (3). Hybrid Embedded Systems. Introduces system hardware and design techniques for embedded and hybrid reconfigurable systems. Intended for those interested in developing projects using hardware description languages to build application-specific computing systems. Industry standards are used for design, development, and debugging.
(Meets with ECEN 5633.)
Credits and Design 3 credit hours: 1 hour of lecture, 2 hours of lab per week; additional hours required outside of formal meeting time. Elective course.
Prerequisite(s) ECEN 2350, Digital Logic
ECEN 3350, Programming of Digital Systems
ECEN 4593, Computer Organization
Textbook None.
Course Objectives This course is intended for those who are interested in investigating emerging design and system technologies, specifically hybrid reconfigurable computing systems that combine processors and reconfigurable Field-Programmable Gate Array (FPGA) fabrics on the same chip. Reconfigurable computing platforms have started to include components with higher integration into the reconfigurable fabric. Early examples of this include components such as multipliers, shifters and the like integrated into a gate-array fabric. More recent implementations include one or more high-performance processors, integrated memory, and multiple clock domains. These chips have sufficient components to build an entire embedded computer system as a combination of reconfigurable fabric and computing core. This mix of components provides a challenge to existing design flows. Projects using Memec boards with Xilinx Virtex-2 Pro systems and industry standard tools are used for development and design.
Topics Covered
  1. Memec system board overview
  2. Verilog introduction, combinational logic
  3. Verilog verification: things that can go wrong, simulation
  4. Xilinx FPGA technology
  5. Implementing Xilinx Virtex-2 Pro core designs
  6. Practical hardware design considerations, interfacing with external hardware.

Last revised: 08-02-11, PM, ARP.