This lab re-introduces you to the
DE0 FPGA board. In this lab, you will be tasked with debugging
some basic verilog code, initializing it onto the DE0 board,
and testing the modules. Functional
Simulation testing and Timing Simulation
testing will both be implemented. For the functional
simulations, you will be required to test it both manually,
and with the use of a testbench. Lastly, you will create a
simple counter that you will simulate in ModelSim and
demonstrate on the DE0.
Figure 1. The DE0 board.
1) You will need to
bring your DE0 board to lab.
2) Review Verilog HDL. Then design a Verilog
module that takes two 4 bit signed (two's complement) inputs, multiplies
them, and outputs the signed (two's complement) result (Inputs: a, b;
Output: y) in Verilog. Additionally, answer the following
question on your pre-lab paper: What is the minimum number of
bits that the signed output must be?
3) Watch these videos
to learn about the Altera Quartus II platform. They will show
you how to create a new project, how to simulate your verilog
code using ModelSim), and how to program your FPGA. Watching
these videos will significantly reduce the
overall time you spend on this lab.
(This lab loosely follows a tutorial available
from Altera: Link.
This tutorial explains how to interact with the wave generation
UI, and will be useful to you during this lab.) Developers are
required to test their designs. To validate a design,
simulations are used to verify that the inputs of a system
results in the expected outputs. There are two main types of
simulations: Functional Simulations check that the
circuit logic is correct, but it does not account for time
delays that inevitably occur in the hardware. Timing
Simulations are a more complex simulation that accounts
for timing delays due to skew within hardware. The latter
simulation is more realistic than the former, however it can
take longer to perform.
Part 1a: Testing and debugging a
multiplexer (mux6) and testing it with Functional Simulations
The German professor, Dr. Waer I. Logue, wants
to create a 6 input multiplexer (mux6) from an already tested
2 input multiplexer, mux2.v. You
will need to create a second module, mux6.v, with inputs [2:0]
s, [5:0] d, and output y, that utilizes the already created
mux2. You should used the DE0 switches and LEDs as inputs and
outputs (see Fig. 2). The truth table for this should be as
Figure 2. Pin Assignments for the DE0.
Before beginning to
make the mux6, it might be helpful to remind yourself how to
program your board using only the mux2.v. Take a few minutes
to create a new project using QuartusII, select your FPGA, set
the simulation software as ModelSim-Altera and select Verilog
HDL as the format. Then add the mux2.v file to the project,
set it as the top-level module, and compile it. Following
this, set the pin assignments using the Pin Planner (DE0 pin
assignments can be found in the DE0 user manual, linked at the
bottom of this lab), recompile to generate a .sof file, and
add this file using the Programmer onto your DE0 board.
Now create a mux6. (Be sure to set the
mux6.v file as the top-level module.) When you have
successfully compiled this, open ModelSim–Altera and create a
new project. Add the mux6.v and mux2.v files into this
project, and compile it. Then select Simulate > Start
Simulation... and select the compiled mux6 module under the work
library. A new window will appear with a blue background.
Right click the inputs and outputs (s, d, and y) and select
Add > To Wave > Selected Signals. When the wave window
appears, click the small icon in the upper left corner to view
the waveform in its own screen. Then set the inputs by right
clicking each input and selecting "Force..." You can then set
the value as 0 or 1. Press OK. Before running the functional
simulation, change the run length to 100 ps. Then press the
Run icon and review the results.
Play around with the UI, and learn what the buttons do. You
can change how the values are displayed by right clicking a
signal and selecting "Radix." You can add a clock signal by
right clicking the signal and clicking "Clock..."
Now, using this manual method, test your mux6 module. When you
feel you have thoroughly tested it, take a screenshot and show
one of the TAs.
Check Off Requirements: For
Part 1a, you need to do the following:
Draw two schematics: One of the mux2 using and/or/xor/nor
gates, the second of a mux6 created out of mux2's.
Demonstrate a working mux6 on the DE0 board using the
switch assignments listed above.
Show a waveform simulation in Altera-Modelsim that shows
functional testing of Fig. 2 truth table for when each "x"
is a 0 using manual manipulation of the waves.
It should look similar (but not exactly) to Fig. 3.
Part 1b: Testing and debugging a
multiplexer (mux6) and testing it with Functional Simulations
Excellent work! As you were doing Part 1a, Dr.
Waer I. Logue found a testbench file that was made for a mux4.
He thinks it will be useful as a starting point for making a
mux6 testbench, and believes that it will greatly speed up the
simulation time for you. Here are the files: testbench.v, and testbenchValues.tv (you
can open the latter using Notepad or Textedit). Take a look at
this testbench and helper file and determine what is happening
in the code. Then re-write it for the mux6 that you have
created. You may also make your own testbench if you would like.
Check Off Requirements: For Part 1b,
you need to do the following:
Show a working testbench that
exhaustively tests your mux6, and displays messages onto the
ModelSim console screen. It should look something like Fig.
3. Simulation for a mux4. Your simulation should
Part 1c: Testing and debugging a
multiplexer (mux6) and testing it with a Timing Simulation
Great job! Dr. Waer I. Logue is
interested in seeing how long the delay is between the inputs and
outputs of the mux6. To do this, you will test the mux6 using a
timing simulation. First go into Quartus II and click Assignments
> Settings. Under EDA Tool Settings click "Simulation," and
select ModelSim-Altera as the Tool name. Set the format as Verilog
HDL, and enable glitch filtering. Press OK and recompile your
project. Then create a new project in ModelSim and import the
mux6.vo file (the .vo file, not
the .v file) into your project. It should be located in the folder
YourProject > simulation > modelsim. Compile your project.
Then click Simulate > Start Simulation... and click the
"Libraries" tab. Add the "cycloneiii_ver" library (ver = verilog).
Then click the "Design" tab and select your mux6 (under the "Work"
library). Press OK. If you get an error, re-select Simulate > Start
Simulation..., and click the "SDF" tab. Browse for the
ProjectName_v.sdo file. Then repeat the tasks for the
"Libraries" and Design" tabs. Press OK. When it fails again,
remove the .sdo file, and re-simulate. It should work this time. If it doesn't, the most likely problem is that you have a file missing from the workspace folder. Read the error in the console window to determine which file is amiss, and place it in the correct folder (most likely needs to go in the project folder).
Notice how there are significantly more objects now in the viewer
window. Select the inputs and outputs (s, d, and y), as well as at
least two of the internal mux2 outputs (see Fig. 4 for
clarification). Stimulate the inputs all at 0, and run your
simulation. This time, you may need to run it for many thousand
picoseconds, as there will be significant time delay. Then
stimulate the inputs all as 1, and repeat the simulation. This
should allow you to estimate the time required to obtain an output
value of 1.
Check Off Requirements:
For Part 1c, you need to do the following:
Using the Timing Simulation, find the time delay between a
change in inputs and the resulting change in the output.
Fig. 4 demonstrates this time delay.
Show that the time delay for an internal variable is less
than the overall input-output time delay via demonstration
in your waveform (see Fig. 4).
– You may find it easiest to edit the code using Quartus
II, compiling here, and then importing/updating these
linked files into Modelsim–Altera.
– You may want to test mux2.v alone to verify that you are
able to communicate with the DE0 board properly.
– You can assign pins using the pin assignment editor.
– To open the waveform view in Modelsim, select View >
– Remember that registers can only be set in one always
Part 2: Counter and Debouncing Switch
Superb job! You've
successfully finished all of Part 1, and you now know how
to simulate using ModelSim, like a professional. In part
2, you will create a counter that displays a binary
summation on the LEDs for each button2 press, where LED0 is the smallest binary number.
You will also implement a reset using button1. In this
lab, you will need to take care of bouncing that occurs
when a switch is pressed/unpressed. It is better to stop
and think about how best to solve the debouncing problem
before writing significant amounts of code. This part 2 is
aimed to help you remember how to code using verilog, as
well as further cement the method of functional testing.
It will be particularly useful for the next lab.
Check Off Requirements: For Part 2, you
need to do the following:
Create a module (using any helper modules) that counts
up in binary using the DE0 LEDs for every button2
press. Pressing button1 should reset every LED
to 0 (off). Demonstrate it working on your DE0 board and
allow for testing by one of the TAs.
Create a Functional waveform
simulation using Modelsim-Altera that demonstrates a
reset and a working counter up to 3'b111. Again, it
will look similar to Fig. 3.
When you are done with these
requirements, please begin running your code. When it is
outputting expected values, find one of the lovely
TAs to check you off.