This laboratory assignment focuses on embedded system software-hardware co-design. The key advantages of a software platform is the flexibility and generality. On the other hand dedicated hardware typically outperforms its software counterpart in terms of performance and efficiency. In this lab, you will bring the software and hardware platforms together in order to leverage the advantages of both.
More specifically, you will filter
a Morse code message from data that has been contaminated by
noise by using a 464 order FIR filter. Previously you learned
how to use the ARM Cortex M0 to control an LED and handle
interrupts. You will use this knowledge to pass information
between the LPCXpresso board and the DE0 (FPGA) board. Then
you will measure how the processing time differs between
running the FIR filter on only the LPCXpresso board vs.
running the FIR filter on an FPGA.
Figure 1. The DE0 board and the LPCXpresso LPC1114 board. You will combine their powers!
2) Review Verilog HDL. Then design a Verilog module that takes two 10 bit signed inputs, multiplies them, and outputs the signed result (Input: a, b; Output: y) in Verilog. Additionally, answer the following question on your pre-lab paper: How many bits must the signed output be?
Story: 5 months ago, NASA sensed a
forced-entry distress signal from the Voyager
2 satellite as it passed the planet XOR. Then, last
week, astronomers identified an extraterrestrial spaceship
coming from the same direction that the Voyager 2 satellite
was travelling towards. The spaceship is massive, and is heading
towards Earth at a rapid velocity! RF scientists detected two signals
coming from the ship, but one signal seemed to be contaminated.
captured a data set of both signals and realized that
the corrupted signal was contaminated by a stray 20 Hz sine wave
from an Earth satellite. The scientists
quickly calculated coefficients that could be used in an FIR
filter to decode the data. Unfortunately, their equipment was
suddenly disabled due to the government shut down, so they
need you to do it for them! They need you to decode the message to
determine if the aliens are friendly or hostile. The
scientists (aware of the Voyager incident and cognizant of the fact
code was sent on the Voyager Golden Record)
found that the uncorrupted signal
counted "...4, 4, 3, 4, 1, 4, 4, 3, 4, 1, 4,
4, 3, 4, 1, 4, 4 ..." in Morse code (using frequency
modulation) with pauses in between each Morse code number
sent. One smart scientist suggested that this might represent
the length of each Morse code character currently thought to
be hidden in the corrupted signal.
Another smart scientist noted that the uncorrupted signal seemed
to repeat over and over and over again.
(Note: Please do not share the decoded message with other groups.)
Here's what you need to do: Firstly, if you still have a resistor connected to your board, replace it with a piece of wire. Figure 2 gives an example of how to set up the communication between the LPC1114 and the DE0, so you can filter the corrupted data. You can follow this protocol or design your own protocol so long as you satisfy the lab requirements. Start a new project and download the lab5.c template file for the LPC side. For the DE0 board, download the lab5.v template. In this lab, you may use additional helper files that are provided in the examples, such as gpio.c and timer32.c. Additionally, when setting up the pin outputs on the FPGA side, be sure and set the voltage for each pin to "3.3 LVCMOS."
Figure 2. Communication protocol between the ARM and the DE0.
Figure 3. Communication depiction between the ARM and the DE0 board.
Set the speed of the test slow enough so that the TAs can see
the output signals.
When you are done with all 5 requirements, begin running your code. Then find one of
the lovely TAs to check you off. (Note: Part 1 counts
as credit for one full lab.)
Great work! You've successfully finished Part 1. The RF
scientists are pleased. Now you will create a 464 order FIR
filter to decode the corrupted data using the FPGA (and the
FPGA internal clock, which runs at 50MHz and has pin
assignment PIN_G21 on the DE0 board). Recall that an FIR
filter looks like that shown in Figure 3.
Figure 3. An FIR filter. Figure 4. FIR bandstop filter amplitude response
The FIR coefficients provided to
you create a bandstop filter at the 20 Hz frequency
as shown in Figure 4. To write the verilog code, it may help
to break the FIR filter down into individual combinational and
sequential logic blocks. If you do this, you will only need to
use the simplest Verilog syntax to describe the circuit.
Lastly, the RF scientists are interested in purchasing the FPGA hardware that you are using for future filtering. However, they first want to know how much better it is relative to the ARM Cortex M0. They have asked you to determine how long it takes for the ARM microprocessor to filter one piece of input data (or how long it takes to process one new data value), and compare this to how long it takes the FPGA to calculate a single bit of data. Thankfully, the RF scientists have provided most of the necessary ARM FIR filter computation software in this .zip file. You may measure this however you wish. Two suggested methods are to 1) use interrupts and/or 2) use the oscilloscope.
***Lab Modification Note: As the largest data number that you are sending is 10 bits (signed) you may find that you will need to modify your Cortex M0 and FPGA code to only send 10 bits. (Thus you will only need 10 clock cycles on the Cortex M0 side.)***
Check Off Requirements: For Part 2, you need to do the following:
Set the speed of the run slow enough so that the TAs can
see the output signal.
When you are done with all 10 requirements, please begin running your code. When
it is outputting expected values, find one of the
lovely TAs to check you off. (Note: Part 2 counts as
credit for one full lab.)
Zip your LPC project files and send this and your Verilog code to firstname.lastname@example.org