DescriptionResearch in VLSI/CAD works toward developing new algorithms and design methodologies to efficiently design VLSI ICs. VLSI researchers leverage knowledge of VLSI circuits and algorithms to devise VLSI design methodologies that allow the VLSI industry to design correct, faster, smaller and more power-efficient integrated circuits. Research in VLSI/CAD has proved to be one of the important reasons for the VLSI boom in recent years. Applications of such research abound in current industrial practice.
The VLSI/CAD program focuses on three areas.
- The effort on formal verification of digital systems addresses the problem of formally verifying a digital design, to ensure it is free of bugs. As part of this effort, the VLSI/CAD group develops and distributes VIS, a formal verification tool which was originally jointly developed with the University of California, Berkeley. VIS utilizes a BDD package called CUDD, which was also developed at the University of Colorado.
- The research effort on VLSI design addresses the design of Deep Sub-micron (DSM) VLSI circuits with the view towards optimizing speed, power, leakage power, area and temperature or process sensitivity of these circuits.
- VLSI design automation research at the University of Colorado also addresses work in CAD algorithms to automate the VLSI design process. These design automation algorithms are targeted towars logic and layout synthesis.
Graduate CoursesECEN 4109/5109, VLSI System Design
ECEN 5129, Simulation Tools for VLSI Systems
ECEN 5139, Formal Verification of VLSI
ECEN 6139, Logic Synthesis of VLSI
Research TopicsCurrent research topics include:
- Formal Verification: BDD-based model checking, SAT-based bounded model checking, fast decision procedures, abstraction-refinement, usability issues.
- VLSI Design: Circuits to speed up on-chip data transfers, alleviate on-chip cross-talk, extreme low power circuits, circuits for low leakage power, process and temperature insensitive circuits, wave pipelined circuits.
- VLSI Design Automation: logic synthesis, layout synthesis, design automation of datapath circuits, hierarchical logic synthesis, fast delay estimation techniques for VLSI ICs.
FacultyA. Bradley (Ph.D., Stanford), formal verification of digital systems, program analysis, computational tools for system analysis
M. Lightner (Ph.D., Carnegie-Mellon) learning technologies, cognitive assistance, assistive technology
Fabio Somenzi (Ph.D., Politecnico di Torino, Italy), formal verification of digital systems, VLSI logic synthesis.
G. Hachtel, (Ph.D., University of California, Berkeley), formal verification of digital systems, VLSI logic synthesis, circuit simulation.