# Integrated Circuit yield

## Circuit Yield

The operating margin of a circuit is defined as the range of device parameters for which the circuit is functional. Margins can be determined by simulating the circuit with a circuit simulator such as SPICE, while varying different device parameters. Assume that such an analysis yields for a single parameter, P, a minimum value, Pmin, and maximum value, Pmax, for which the circuit is functional. Let us also assume that the actual distribution of this device parameter is gaussian, so that the optimal average value of the parameter P is halfway between Pmin and Pmax as shown in the figure below.

yield1.gif
Fig. Gaussian distribution of a parameter P. The parameter range for which the circuit is functional is between Pmin and Pmax
The probability that for N devices their parameter P lies within the two boundaries is then given by:
(eqy1)
where we assumed their is no statistical correlation between the parameter P of two different devices. Using the first two terms of the binomial expansion this can be approximated for large values of N as:
(y2)
Both expressions are plotted in Fig.2 for different values of N. A simple rule of thumb can be derived from equation y2 namely that a yield of 80 % occurs for:
(y3)
This transcendental equation can be easily solved by iteration yielding the following values for a as calculated for different values of N:
 N 103 104 105 106 a 3.73 4.28 4.76 5.21
This means that in order to obtain an 80 % circuit yield for a circuit in which only one parameter varies, and assuming the distribution of this parameter to be gaussian with spread s, the circuit margin must be at least 3.73s for a circuit with one thousand devices and 5.21s for a circuit with one million devices. This explains the common 3s design rule for LSI (Large Scale Integration) circuits which has become a 5s design rule for VLSI (Very Large Scale Integration) circuits.

yield.xls - yield.gif
Fig. Circuit yield as a function of the normalized parameter range (Pmax - Pmin)/2s
Problem:
For an NMOS aluminum gate transistor on a 1016 cm-3. substrate with 10 nm gate oxide and a threshold voltage of 150 mV, find the spread of the oxide thickness corresponding to a threshold variation of 20 mV.

## Process Yield

Process yield is the more commonly quoted yield associated with the fabrication of integrated circuits. Referred to is the yield reduction caused by physical defects on the wafer circuit which cause the adjacent device and therefore also the circuit to fail. The probability that one chip contains exactly k defects, while the wafer contains N circuits as well as n defects, is given by:
(y4)
This expression is obtained by finding the total number of combinations of putting the remaining n-k defects in the remaining N-1 chips devided by the total number of combinations to put the n defects into N chips. This does not account for the possibility of exchanging defects while maintaining the same number k on the chip of interest. We therefore multiply that ratio with the total number of ways to exchange any of the n defects so that the same number, k, remain on the one chip so that n-k can be found on the rest of the wafer. The above equation, for large n and N and a small number of defects k, using the Stirling approximation yielding:
(y5)
which also equals the Poisson distribution. The corresponding yield, Y, is given by the probability that the circuit has no defect (k = 0) so that
(y6)
This result can be further extended to non-uniform defect distributions by summing the expression for a constant distribution applied to a section DD and weighted by the probability of having a particular defect density, f(D), yielding:
(y7)
which in the limit where DD goes to zero can be expressed as a function of the following integral:
(y8)

© Bart J. Van Zeghbroeck, 1997