Publications

Publications including journals and conference/workshop papers.

2011  Techniques to Leverage Data-Parallel GPU Acceleration for Computer Vision Algorithms
Allen Nichols
M.S. Thesis, Department of Electrical Engineering, University of Colorado Denver. May 2011
[ ABSTRACT ][ PDF ]

2010  OE+IOE: A Novel Turn Model Based Fault Tolerant Routing Scheme for Networks-on-Chip
Yong Zhu, Sudeep Pasricha, Dan Connors
Accepted for publication in IEEE International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), 2010
[ ABSTRACT ] [ PDF ]

Modeling Ion Channel Kinetics with High-Performance GPU Processors
Allison Gehrke, Katherine Rennie, Timothy Benke, Dan Connors, Ilkyeun Ra
Accepted for publication in IEEE International Conference on High-Performance Computing and Communications (HPCC 2010)
[ ABSTRACT ]

Failure Estimation for Partial TMR Mitigated Designs in a Virtex-4 FPGA
Scott Arlo Anderson
M.S. Thesis, Department of Electrical Engineering, University of Colorado Denver. May 2010
[ ABSTRACT ][ PDF ]

2009  Characterizing the Use of Program Vulnerability Factors for Studying Transient Fault Tolerance in Multi-core Architectures
Robert Kost, Daniel Connors, Sudeep Pasricha.
Proceedings of the 2009 International Conference on Dependable Systems and Networks (DSN) Workshop on Compiler and Architectural Techniques for Application Reliability and Security (CATARS) June, 2009.
[ ABSTRACT ] [ PDF ]

Enabling Dynamic Voltage and Frequency Scaling in Multicore Architectures
Amithash Prasad
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado. August, 2009.
[ ABSTRACT ][ PDF ]

2008  PLR: A Software Approach to Transient Fault Tolerance for Multi-Core Architectures
Alex Shye, Joseph Blomstedt, Tipp Moseley, Vijay Janapa Reddi, Daniel A. Connors.
IEEE Transactions on Dependable and Secure Computing (TDSC) December,
[ ABSTRACT ][ PDF ]

Optimizing Consistency Checking for Memory-Intensive Transactions with DracoSTM
Justin Gottschlich, Daniel A. Connors.
Proceedings of the 2008 ACM Symposium on Principles of Distributed Computing (PODC) August, 2008.
[ ABSTRACT ][ PDF ]

C++ Move Semantics for Exception Safety and Optimization in Software Transactional Memory Libraries
Justin Gottschlich, Jeremy Siek, Daniel A. Connors.
Proceedings of the 2008 International Workshop on Implementation, Compilation, Optimization of Object-Oriented Languages, Programs and Systems (ICOOOLPS 2008) July, 2008.
[ ABSTRACT ][ PDF ]

A Framework for Efficiently Analyzing Architecture-Level Fault Tolerance Behavior in Applications
Harshad Sane
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado. May, 2008.
[ ABSTRACT ][ PDF ]

A Unified Approach to Adaptive Code Selection for Modern Systems
Joseph Blomstedt
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado. May, 2008.
[ ABSTRACT ][ PDF ]

Cardinal: A Framework for Performance Modeling and Prediction of Application Execution
Sam Strom
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado. May, 2008.
[ ABSTRACT ][ PDF ]

Extending Contention Managers for User-Defined Priority-Based Transactions
Justin Gottschlich , Daniel A. Connors.
Proceedings of the 2008 Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods April, 2008.
[ ABSTRACT ][ PDF ]

2007  Discovering the Runtime Structure of Software with Probabilistic Generative Models
Scott Richardson, Michael Otte, Michael C. Mozer, Amer Diwan, Daniel A. Connors
Proceedings of the 2007 International Symposium on Neural Information Processing Systems Workshop for Statistical Learning Techniques for Solving Systems Problems (MLSys) December, 2007.
[ ABSTRACT ][ PDF ]

Simulation and Characterization of Inter-Process Interference on Mulithtreaded and Multicore Architectures
Joshua Kihm.
Ph.D. Dissertation, Department of Electrical and Computer Engineering, University of Colorado. November, 2007.
[ ABSTRACT ] [ PDF ]

Exploration of Lock-Based Software Transactional Memory
Justin Gottschlich.
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado. November, 2007.
[ ABSTRACT ][ PDF ]

DracoSTM: A Practical C++ Approach to Software Transactional Memory
Justin Gottschlich , Daniel A. Connors.
Proceedings of the 2007 The ACM SIGPLAN Symposium on Library-Centric Software Design (LCSD) October, 2007.
[ ABSTRACT ][ PDF ]

An Adaptive Fault-Tolerant Memory System for FPGA-based Architectures in the Space Environment
Dan Fay, Alex Shye, Sayantan Bhattachrarya, Steve Wichmann, and Daniel A. Connors
2007 NASA/ESA Conference on Adaptive Hardware Systems August, 2007.
[ ABSTRACT ][ PDF ]

Investigating the Potential of a GPU-based Math Library
Daniel Fay.
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado. August, 2007.
[ ABSTRACT ][ PDF ]

A Dynamically Reconfigurable Pattern Recognition FPGA Architecture
Scott Cbell and Daniel A. Connors
2007 International Conference on Reconfigurable Systems and Algorithms July, 2007.
[ ABSTRACT ]

Teaching Fault Tolerant FPGA Design for Aerospace Applications
Dan Fay, Scott Cbell, Greg Miller, and Daniel A. Connors
2007 International Conference on Microelectronic Systems Education June, 2007.
[ ABSTRACT ]

Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Joseph Blomstedt, Daniel A. Connors.
Proceedings of the 2007 International Conference on Dependable Systems and Networks (DSN). June, 2007.
[ ABSTRACT ][ PDF ]

CoGS-Sim: Co-Phase Guided Small-Sle Simulation of Multithreaded and Multicore Architectures
Joshua Kihm, Daniel A. Connors.
Proceedings of The Workshop on Modeling, Benchmarking, and Simulation (MoBS 07) held in conjunction with ISCA-34. June, 2007.
[ ABSTRACT ][ PDF ]

Profile Merging and Code Versioning for Automated Profile Guided Optimization Systems
Rahul Saxena.
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado. May, 2007.
[ ABSTRACT ][ PDF ]

Identifying Potential Parallelism via Loop-centric Profiling
Tipp Moseley, Daniel A. Connors, Dirk Grunwald, Ramesh Peri
Proceedings of the 2007 International Conference on Computing Frontiers (CF). May, 2007.
[ ABSTRACT ][ PDF ]

Phase-Guided Small Sle Simulation
Joshua Kihm, Sam Strom, Daniel A. Connors.
Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) April, 2007.
[ ABSTRACT ][ PDF ]

Persistent Code Caching: Exploiting Code Reuse Across Executions and Applications
Vijay Janapa Reddi, Robert Cohn, Michael Smith, Daniel A. Connors.
Proceedings of the 5th International Conference on Code Generation and Optimization (CGO). March, 2007.
[ ABSTRACT ][ PDF ]

Model Based Load Indices (MBLI) for Scientific Simulation
Stefan Muszala
Ph.D. Dissertation, Department of Electrical and Computer Engineering, University of Colorado. January, 2007.
[ ABSTRACT ][ PDF ]

2006  A Detailed Study of the Numerical Accuracy of GPU-Implemented Math Functions
Dan Fay, Ali Sazegari, Daniel A. Connors.
Supercomputing '06 Workshop on General-Purpose GPU Computing: Practice And Experience. November, 2006.
[ ABSTRACT ][ PDF ]

Understanding Cache Interference
Alex Settle.
Ph.D. Dissertation, Department of Electrical and Computer Engineering, University of Colorado. November, 2006.
[ ABSTRACT ][ PDF ]

Using LoopProf to Identify Parallelism in Sequential Programs
Tipp Moseley, Vasanth Tovinkere, Ram Ramanujan, Daniel A. Connors, and Dirk Grunwald
Proceedings of the Workshop on Binary Instrumentation and Applications (WBIA). October, 2006.
[ ABSTRACT ][ PDF ]

Transient Fault Tolerance via Dynamic Process Redundancy
Alex Shye, Vijay Janapa Reddi, Tipp Moseley, and Daniel A. Connors
Proceedings of the Workshop on Binary Instrumentation and Applications (WBIA). October, 2006.
[ ABSTRACT ][ PDF ]

Partial Reconfiguration Across FPGAs
Steve Wichman, Sammit Adyha, Scott Ahrens, Rohan Ambli, Brad Alcorn, Dan Fay, Daniel A. Connors
Proceedings of the International Conference on Military and Aerospace Programmable Logic Devices (MAPLD). September, 2006.
[ ABSTRACT ][ PDF ]

Hardware-Compiler Co-Design for Adjustable Data Power Savings
Hillery C. Hunter, Erik M. Nystrom, Daniel A. Connors, Wen-mei W. Hwu.
International Journal of Embedded Systems. June, 2006.
[ ABSTRACT ][ PDF ]

An Evolving Curriculum to Match the Evolution of Reconfigurable Computing Platforms
Graham Schelle, Dan Fay, Dirk Grunwald, Daniel A. Connors and John Bennett
The 1st International Workshop on Reconfigurable Computing Education (RC education 2006). March, 2006.
[ ABSTRACT ][ PDF ]

Improved Stride Prefetching using Extrinsic Stream Characteristics
Hassan Al-Sukhni, Jim Holt, and Daniel A. Connors.
IEEE International Symposium on Performance Analysis of Systems and Software. March, 2006.
[ ABSTRACT ][ PDF ]

The Design of Cost-Effective Stride-Prefetching for Modern Processors
Hassan Al-Sukhni, James Holt, Daniel A. Connors, Mike Snyder, Matt Smittle, Brian Grayson
4th Workshop on Memory Performance Issues (WMPI-2006) February, 2006.
[ ABSTRACT ][ PDF ]

Exploiting Parallelism and Structure to Accelerate the Simulation of Chip Multi-processors
David Penry, Dan Fay, Graham Schelle, Ryan Wells, David I. August, and Daniel A. Connors.
12th International Symposium on High-Performance Computer Architecture. February, 2006.
[ ABSTRACT ][ PDF ]

Dynamic Compiler Driven Control for Microprocessor Energy and Performance
Qiang Wu, Vijay Janapa Reddi, Youfeng Wu, Daniel A. Connors, David Brooks, Margaret Martonosi, Douglas W. Clark
IEEE Micro's Top Picks in Computer Architecture Conferences. January, 2006.
[ ABSTRACT ][ PDF ]

2005  A Dynamically Reconfigurable Cache for Multithreaded Processors
Alex Settle, Daniel A. Connors, Enric Gibert, Antonio Gonzalez.
Journal of Embedded Computing: Special Issue on Single-Chip Multi-core Architectures. December, 2005.
[ ABSTRACT ][ PDF ]

Deploying Dynamic Code Transformation in Modern Computing Environments
Vijay Janapa Reddi.
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado. November, 2005.
[ ABSTRACT ][ PDF ]

A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
Qiang Wu, Vijay Janapa Reddi, Youfeng Wu, Daniel A. Connors, David Brooks, Margaret Martonosi, Douglas W. Clark
Proceedings of the 38th IEEE/ACM International Symposium on Microarchitecture (MICRO). November, 2005.
[ ABSTRACT ][ PDF ]

Hardware-Compiler Co-Design for Adjustable Data Power Savings
Hillery C. Hunter, Erik M. Nystrom, Daniel A. Connors, Wen-mei W. Hwu.
Proceedings of the 7th Workshop on Media and Streaming Processors. November, 2005.
[ ABSTRACT ][ PDF ]

Chip-Multiprocessor Scalability for Single-Threaded Applications
Neil Vachharajani, Matthew Iyer, Chinmay Ashok, David August, Daniel A. Connors, Manish Vachharajani
Proceedings of the 2005 Workshop on Design, Architecture, and Simulation of Chip Multi-Processors (dasCMP). November, 2005.
[ ABSTRACT ][ PDF ]

Identifying and Exploiting Memory Access Characteristics for Prefetching Linked Data Structures
Hassan Al-Sukhni.
Ph.D. Dissertation, Department of Electrical and Computer Engineering, University of Colorado. November, 2005.
[ ABSTRACT ][ PDF ]

Methods for Modeling Resource Contention on Simultaneous Multithreading Processors
Tipp Moseley, Joshua Kihm, Daniel A. Connors, Dirk Grunwald.
Proceedings of the 2005 International Conference on Computer Design (ICCD). October, 2005.
[ ABSTRACT ][ PDF ][ Slides PDF ]

Code Coverage Testing Using Hardware Performance Monitoring Support
Alex Shye, Matthew Iyer, Vijay Janapa Reddi, Daniel A. Connors.
Proceedings of the 6th International Symposium on Automated and Analysis-Driven Debugging (AADEBUG). September, 2005.
[ ABSTRACT ][ PDF ]

Statistical Simulation of Multithreaded Architectures
Joshua Kihm and Daniel A. Connors.
Proceedings of 13th Annual Meeting of the IEEE International Symposium on Modeling, Analysis, and Simulation of Computer Systems. September, 2005.
[ ABSTRACT ][ PDF ]

Persistence in Dynamic Code Transformation Systems
Vijay Janapa Reddi, Daniel A. Connors and Robert S. Cohn.
Proceedings of the Workshop on Binary Instrumentation and Applications (WBIA). September, 2005.
[ ABSTRACT ][ PDF ]

The Promise of Load-Balancing the Parameterization of Moist Convection on Multi-Processor Systems
S.P. Muszala, J.J. Hack, D.A. Connors, G. Alaghband
Journal of Atmospheric and Oceanic Technology. July, 2005.
[ ABSTRACT ][ PDF ]

Understanding the Impact of Inter-Thread Cache Interference on ILP in Modern SMT Processors
Joshua Kihm, Alex Settle, Andy Janiszewski, Daniel A. Connors.
The Journal of Instruction Level Parallelism (JILP), Volume 7. June, 2005.
[ ABSTRACT ][ PDF ]

A Mathematical Model for Accurately Balancing Co-Phase Effects in Simulated Multithreaded Systems
Joshua Kihm, Tipp Moseley, Daniel A. Connors.
Proceedings of The Workshop on Modeling, Benchmarking, and Simulation (MoBS 05) held in conjunction with ISCA-32. May, 2005.
[ ABSTRACT ][ PDF ]

Dynamic Run-time Architecture Techniques for Enabling Continuous Optimization
Tipp Moseley, Alex Shye, Vijay Janapa Reddi, Matthew Iyer, Dan Fay, Joshua L. Kihm, Alex Settle, Dirk Grunwald, Daniel A. Connors.
Proceedings of the 2005 International Conference on Computing Frontiers (CF). May, 2005.
[ ABSTRACT ][ PDF ][ Slides PDF ]

Exploring the Potential of Performance Monitoring Hardware to Support Run-time Optimization
Alex Shye.
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado. May, 2005.
[ ABSTRACT ][ PDF ]

Analysis of Hardware Acceleration in Reconfigurable Embedded Systems
Mathew Ouellette and Daniel A. Connors
Proceedings of the 12th Reconfigurable Architectures Workshop (RAW 2005). April, 2005.
[ ABSTRACT ][ PDF ]

Finding Parallelism for Future EPIC Machines
Matthew Iyer, Chinmay Ashok, Josh Stone, Neil Vachharajani, Daniel A. Connors, Manish Vachharajani.
Proceedings of the 4th Workshop on Explicitly Parallel Instruction Computing. March, 2005.
[ ABSTRACT ][ PDF ]

Analysis of Path Profiling Information Generated with Performance Monitoring Hardware
Alex Shye, Matthew Iyer, Tipp Moseley, Dan Fay, Vijay Janapa Reddi, Daniel A. Connors.
Proceedings of the 9th Workshop on Interaction between Compilers and Computer Architecture (INTERACT). February, 2005.
[ ABSTRACT ][ PDF ]

2004  Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling
Joshua Kihm, Daniel A. Connors.
Proceedings of the 2004 International Conference on Computer Design. October, 2004.
[ ABSTRACT ][ PDF ]

Architectural Support for Enhanced SMT Job Scheduling
Alex Settle, Joshua Kihm, Andy Janiszewski, Daniel A. Connors.
Proceedings of the 13th International Symposium on Parallel Architectures and Compilation Techniques. October, 2004.
[ ABSTRACT ][ PDF ]

A Very Fast Simulated Annealing Scheduler for Radioactive Transfer Data in Climate Models
S.P. Muszala, G. Alaghband, D.A. Connors, J.J. Hack.
Proceedings of the 17th International Conference on Parallel and Distributed Computing Systems (PDCS). September, 2004.
[ ABSTRACT ][ PDF ]

Predictable Fine Grained Cache Behavior for Enhanced Simulaneous Multithreading (SMT) Scheduling
Joshua Kihm, Andy Janiszewski, Daniel A. Connors.
Proceedings of the 2004 Conference on Computing, Communications, and Technologies. August, 2004.
[ ABSTRACT ][ PDF ]

PIN: A Binary Instrumentation Tool in Computer Architecture Research and Education
Vijay Janapa Reddi, Alex Settle, Daniel A. Connors, Robert Cohn.
Proceedings of the 7th International Workshop on Computer Architecture Education (WCAE). June, 2004.
[ ABSTRACT ][ PDF ]

Compiler Controlled Register Stack Management for the Intel Itanium Architecture
Alex Settle, Daniel Lavery, Gerolf Hoflehner, Daniel A. Connors.
Proceedings of the 3rd Workshop on Explicitly Parallel Instruction Computing Architectures and Compiler Techniques. March, 2004.
[ ABSTRACT ][ PDF ]

2003  Using Existing Performance Monitoring Hardware to Enable Power Prediction in Microprocessors
Garret Holthaus
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado. December, 2003.
[ ABSTRACT ][ PDF ]

Compiler-Directed Content-Based Prefetching for Dynamic Data Structures.
Hassan Al-Sukhni, Ian Bratt, Daniel A. Connors.
Proceedings of the 12th International Symposium on Parallel Architectures and Compiler Techniques. October, 2003.
[ ABSTRACT ][ PDF ]

Analysis and Design of Architecture Systems for Speech Recognition on Modern Handheld-Computing Devices.
Andreas Hagen, Bryan Pellom, Daniel A. Connors.
Proceedings of the of the 11th International Symposium on Hardware/Software Codesign. October, 2003.
[ ABSTRACT ][ PDF ]

Vertical Optimization of Particle in Cell Code Simulation
Viktor Przebinda
M.S. Thesis, Department of Electrical and Computer Engineering, University of Colorado. May, 2003.
[ ABSTRACT ][ PDF ]

Optimization for the Intel Itanium Architecture Register Stack.
Alex Settle, Daniel Lavery, Gerolf Hoflehner, Daniel A. Connors.
Proceedings of the 1st Conference on Code Generation and Optimization. March, 2003.
[ ABSTRACT ][ PDF ]

Compiler-Directed Resource Management for Active Code Regions.
Ravikrishnan Sree, Ian Bratt, Alex Settle, Daniel A. Connors.
Proceedings of the 7th Workshop on Interaction between Compilers and Computer Architecture. February, 2003.
[ ABSTRACT ][ PDF ]

2001  Predicate-Based Transformations to Eliminate Control and Data-Irrelevant Cache Misses.
Alex Settle, Ian Bratt, Daniel A. Connors.
Proceedings of the 1st Workshop on Explicitly Parallel Instruction Computing Architectures and Compilers. December, 2001.
[ ABSTRACT ][ PDF ]

pre- 2000  Hardware Support for Dynamic Activation of Compiler-Directed Computation Reuse.
Daniel A. Connors, Hiller C. Hunter, Ben-Chung Cheng, Wen-mei W. Hwu.
Proceedings of the 9th International Conference on Architecture Support for Programming Languages and Operating Systems. November, 2000.
[ ABSTRACT ][ PDF ]

Eliminating Dynamic Computation Redundancy.
Daniel A. Connors.
Ph.D. Dissertation, Department of Electrical and Computer Engineering, University of Illinois, Urbana IL. May, 2000.
[ ABSTRACT ][ PDF ]

Compiler-Directed Early Load-Address Generation.
Ben-Chung Cheng, Daniel A. Connors, Wen-mei W. Hwu.
Proceedings of the 31th International Symposium on Microarchitecture. December, 1999.
[ ABSTRACT ][ PDF ]

Run-Time Cache Bypassing.
T. L. Johnson, M. C. Merten, Daniel A. Connors, W. W. Hwu.
IEEE Transactions on Computers. December, 1999.
[ ABSTRACT ][ PDF ]

Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results.
Daniel A. Connors, Wen-mei W. Hwu.
Proceedings of the 32nd International Symposium on Microarchitecture. November, 1999.
[ ABSTRACT ][ PDF ]

An Architecture Framework for Introducing Predicated Execution into Embedded Microprocessors.
Daniel A. Connors, Jean-Michel Puiatti, David I. August, Kevin M. Crozier, Wen-mei W. Hwu.
Proceedings of the 5th International Euro-Par Conference. August, 1999.
[ ABSTRACT ][ PDF ]

The Program Decision Logic Approach to Predicated Execution.
David I. August, John W. Sias, Jean-Michel Puiatti, Scott A. Mahlke, Daniel A. Connors, Kevin M. Crozier, Wen-mei W. Hwu.
Proceedings of the 26th International Symposium on Computer Architecture. May, 1999.
[ ABSTRACT ][ PDF ]

A Software-Oriented Floating-Point Format for Enhancing Automotive Control Systems.
Daniel A. Connors, Yoji Yamada, Wen-mei W. Hwu.
Workshop on Compiler and Architecture Support for Embedded Computing Systems (CASES98). December, 1998.
[ ABSTRACT ][ PDF ]

Integrated Predicated and Speculative Execution in the IMPACT EPIC Archtecture.
David I. August, Daniel A. Connors, Scott A. Mahlke, John W. Sias, Kevin M. Crozier, Ben-Chung Cheng, Patrick R. Eaton, Qudus B. Olaniran, Wen-mei W. Hwu.
Proceedings of the 25th International Symposium on Computer Architecture. July, 1998.
[ ABSTRACT ][ PDF ]

Run-time Adaptive Cache Management.
Teresa L. Johnson, Daniel A. Connors, Wen-mei W. Hwu.
Proceedings of the 31st Annual Hawaii International Conference on system Sciences. January, 1998.
[ ABSTRACT ][ PDF ]

Memory Profiling for Directing Data Speculative Optimizations and Scheduling.
Daniel A. Connors.
M.S. Thesis, Department of Electrical and Computer Engineering, University of Illinois, Urbana IL. May, 1997.
[ ABSTRACT ][ PDF ]

Architectural Support Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results.
David I. August, Daniel A. Connors, John Gyllenhaal, Wen-mei W. Hwu.
The 3rd International Symposium on High-Performance Computer Architecture. February, 1997.
[ ABSTRACT ][ PDF ]