Counter/Timer Details

Background

Counter/Timers are devices that do what their name implies; they can be used to count events or signals external to the system, or the can be used to time activities. A counter/timer is a hardware device that must be initialized or programmed just as other I/O devices. Normally a counter/timer is wired so that its output can be read by a program, or the counter/timer interrupts the CPU on some condition.

The behavior of the counter/timer on the MB5 is summarized below. A more detailed description of the counter/timer chip maybe found in the PDF version of the data sheet.

Counter/Timers

The counter/timer chip on the MB5 contains 3 identical 16-bit counter/timers known as CT0, CT1 and CT2. Each counter/timer has a clock input that runs at 8MHz, or a 125 nsec period. The counters each have a gate input that is controlled by writing a byte to location $A00001 (this location is defined as GATE in the file counter.ah. The gate input can be used to enable or disable counting. A 1 at the gate input enables counting, while a 0 disables, or stops, the counter. The output of each counters is connected in such a way as to generate an interrupt when 1 to 0 transition occurs on the output. The interrupt level and location where the autovector interrupt is set to start executing code are given in the table below. In addition, the bit corresponding to the gate input for each counter is also given.

	Interrupt Level	Vector Location	Gate Bit
CT0	6	$100028	0
CT1	4	$100018	1
CT2	3	$100010	2

Each of the counter/timers can be programmed to have one of five different behaviors (modes, described below) by writing a byte to the relative port address of 7. This relative address is denoted by the symbol CTCMD in file counter.ah.

SC is the counter number, in the range 0-2.

RL defines how the counter is to be read or loaded:

RL=0 means that the current value of the counter is to be latched for later reading. With this value of RL, the contents of fields MODE and BCD are irrelevant; latching the counter value is the only effect of a command with RL=0.
RL=1 means that any subsequent read or load command for the specified counter consists of reading or writing a single byte at the appropriate relative port address. The least significant byte of the counter is read or loaded.
RL=2 means that any subsequent read or load command for the specified counter consists of reading or writing a single byte at the appropriate relative port address. The most significant byte of the counter is read or loaded.
RL=3 means that any subsequent read or load command for the specified counter consists of reading or writing two successive bytes at the appropriate relative port address. The least significant byte is transferred first and the most significant byte is transferred second.

Note that the counter value is 16 bits, regardless of the way in which it is read or loaded. Thus when RL=2, indicating that the most significant byte is to be read or loaded, and the value 1 is loaded, the counter value is actually 256.

MODE, in the range 0-5, defines the subsequent behavior of the counter/timer. The detailed descriptions of the behavior in each mode are given below. MODE is only effective if RL is not equal to 0.

BCD selects whether the counter contents are regarded as a 16-bit binary number (BCD=0) or a 4-digit binary-coded decimal number (BCD=1). If BCD=0 the maximum possible count is 65,535 and if BCD=1 the maximum possible count is 9,999.

CTi must be programmed by writing a command byte with SC=i and RL nonzero to the counter/timer command register (CTCMD) before attempting any use of CTi. When the computer is powered up, all of the counter/timers are in undefined states with undefined counts. If a counter is used before being programmed, the results cannot be predicted.

Reading and Loading Counter Values

Counter values are read and loaded by reading and writing a byte at relative port addresses 1, 3 and 5. These relative addresses are denoted by the symbols CT0, CT1 and CT2 (respectively) in file counter.ah.

The read and load operations must be exactly those specified for the given counter by the RL field of the byte used to program that counter (above). For example, if RL=3 in the byte used to program CT0, then a value is loaded into CT0 by a sequence of two move.b instructions. The first move.b instruction loads the least significant byte of the value, and the second move.b instruction loads the most significant byte.

Before reading a counter, you should latch the counter value by writing a control byte with SC specifying the number of the counter to be read and RL=0. The contents of the remaining fields are arbitrary. Writing this byte to CTCMD will not change the counter's behavior; it simply latches the current counter value.

Mode 0: Transition on Terminal Count

When a control byte with RL nonzero and MODE=0 is written to CTCMD, the output for the selected counter is set to 0. It remains 0 until a count is loaded into the counter, and the counter has decremented that count to 0. When the count reaches 0, the output changes to 1 and remains at 1 until a new count has been loaded. Completion of the loading of the new count sets the output 0, where it remains until the counter has decremented that count to 0.

If the counter is reloaded before it has decremented the previous count to 0, decrementing begins anew with the new count. Thus it is possible to prevent the output from ever becoming 1 by continually reloading the counter.

Mode 1: Programmable One-Shot

When a control byte with RL nonzero and MODE=1 is written to CTCMD, the output for the selected counter is set to 1. The output does not change when a count is loaded into the counter.

When the gate input changes from 0 to 1, the output is set to 0. This transition of the gate also resets the counter from the loaded value, and the counter starts decrementing. When the count reaches 0, the output changes to 1 and remains at 1 until the gate input again changes from 0 to 1.

Each transition of the gate from 0 to 1 resets the counter. Thus it is possible to prevent the output from ever becoming 1 by continually pulsing the gate input.

Reloading the count has no effect until the next transition of the gate from 0 to 1. At that point the counter will be reset to the newly-loaded value.

Mode 2: Rate Generator

When a control byte with RL nonzero and MODE=2 is written to CTCMD, the output for the selected counter is set to 1. The output goes to 0 for one period of the input clock when a value is loaded into the counter, and then returns to 1. After the counter decrements to 0, the output goes to 0 for one period of the input clock and the counter is reset to the value loaded. Thus the time interval from the beginning of one output pulse to the beginning of the next is equal to the number of input clock periods represented by the value loaded into the counter.

If a new value is loaded into the counter, it has no effect on the current interval. When the counter is reset at the end of the interval, however, it will be reset to the new value. Thus the new value will control the length of subsequent intervals.

If the gate input is 0, the output is held at 1. When the gate input changes from 0 to 1, the counter is reset to the value loaded but the output remains 1 until the counter decrements to 0. Thus the gate can be used to synchronize the output pulses to some external event.

Mode 3: Square-Wave Rate Generator

When a control byte with RL nonzero and MODE=3 is written to CTCMD, the output for the selected counter is set to 1. The output goes to 0 when a value is loaded into the counter. Let N be the value that is loaded.

If N is even, the output will remain 0 for N/2 periods of the input clock and then change to 1 for the next N/2 periods of the input clock. The counter is then reset from the loaded value, the output is set to 0, and the process is repeated.

If N is odd, the output will remain 0 for (N-1)/2 periods of the input clock and then change to 1 for the next (N+1)/2 periods of the input clock. The counter is then reset from the loaded value, the output is set to 0, and the process is repeated.

The gate input must be set to 1 for the counter to count. When the gate input goes to a 0, the counter output goes to a 1 value and the counter is reloaded with the initial count value.

Mode 4: Software-Triggered Strobe

When a control byte with RL nonzero and MODE=4 is written to CTCMD, the output for the selected counter is set to 1. When the counter is loaded, it begins to decrement. The output goes to 0 for one period of the input clock after the counter decrements to 0. Thus mode 4 simply implements a delay function triggered by the CPU program.

If the counter is reloaded during counting, the count is set to the new value on the next input clock pulse. The output remains at 1. By reloading the counter periodically, the output can be kept at 1 indefinitely.

Counting is inhibited when the gate input is held at 0, but there is no change in the count itself.

Mode 5: Hardware-Triggered Strobe

When a control byte with RL nonzero and MODE=5 is written to CTCMD, the output for the selected counter is set to 1. When the gate input changes from 0 to 1, the counter begins to decrement. The output goes to 0 for one period of the input clock after the counter decrements to 0. Thus mode 4 simply implements a delay function triggered by an external event.

If the gate input changes from 0 to 1 during counting, the count is reset to the loaded value. The output remains at 1. By changing the gate periodically, the output can be kept at 1 indefinitely.

Reloading the counter has no effect until the next time the gate input changes from 0 to 1. At that point the counter will be reset to the new value.

Instructor

Revision $Revision: 1.2 $ ($Date: 2004/02/27 03:56:40 $)