; $Id: uart.ah,v 1.11 2004/02/11 20:18:37 ecen2120 Exp $

UART1	equ	$200000	UART1 port base address
U1INT	equ	$100030	UART1 interrupt address
UART2	equ	$900000	UART2 port base address
U2INT	equ	$100020	UART2 interrupt address
UCLOCK	equ	115200	MB5 UART clock frequency

; Register definitions for the 16550 UART

RBR	equ	$1	Read buffer register READ ONLY
THR	equ	$1	Transmit holding register WRITE ONLY
DLL	equ	$1	Least-significant baud rate divisor byte WRITE ONLY
IER	equ	$3	Interrupt Enable Register READ AND WRITE
DLM	equ	$3	Most-significant baud rate divisor byte WRITE ONLY
IIR	equ	$5	Interrupt identification register READ ONLY
LCR	equ	$7	Line control register READ AND WRITE
MCR	equ	$9	Modem control register READ AND WRITE
LSR	equ	$B	Line status register READ ONLY
MSR	equ	$D	Modem status register READ ONLY
SCR	equ	$F	Scratch register READ AND WRITE

; Bit definitions for the 16550 UART

;			LCR
DLAB	equ	7	Divisor latch access bit
SBRK	equ	6	Set break
FP	equ	5	Fixed parity
EP	equ	4	Even parity
EPS	equ	4	Even parity select
PEN	equ	3	Parity enable
XSB	equ	2	Extra stop bit
STB	equ	2	Number of stop bits
CLEN	equ	0	Character length

CLEN5	equ	0	5 information bits
CLEN6	equ	1	6 information bits
CLEN7	equ	2	7 information bits
CLEN8	equ	3	8 information bits

;			LSR
TEMT	equ	6	Transmitter empty
TxST	equ	6	Transmit complete
THRE	equ	5	Transmitter holding register empty
TxRA	equ	5	Transmit ready
BI	equ	4	Break interrupt
BKD	equ	4	Break detected
FE	equ	3	Framing error
PE	equ	2	Parity error
OE	equ	1	Overrun error
DR	equ	0	Data ready
RxDA	equ	0	Data available

;			MCR
LC	equ	4	Loopback control
OUT2	equ	3	System-defined
OUT1	equ	2	System-defined
RTS	equ	1	Request to send
DTR	equ	0	Data terminal ready

;			MSR
CD	equ	7	Carrier detect
DCD	equ	7	Data carrier detect
RI	equ	6	Ring indicator
DSR	equ	5	Data set ready
CTS	equ	4	Clear to send
CDC	equ	3	CD has changed
DDCD	equ	3	Delta data carrier detect
RING	equ	2	RI has changed
TERI	equ	2	Trailing edge ring indicator
DSRC	equ	1	DSR has changed
DDSR	equ	1	Delta data set ready
CTSC	equ	0	CTS has changed
DCTS	equ	0	Delta clear to send

;			IER
MCHE	equ	3	Modem change enable
EDSSI	equ	3	Enable modem status interrupt
RERE	equ	2	Receive error enable
ELSI	equ	2	Enable receiver line status interrupt
TDEE	equ	1	Transmit data empty enable
ETBEI	equ	1	Enable transmitter holding register empty interrupt
RDAE	equ	0	Receive data full enable
ERBFI	equ	0	Enable received data available interrupt

;			IIR
AI	equ	1	Active interrupt
AIMSK	equ	6	Active interrupt mask
IPN	equ	0	Interrupt pending