Name:______________________________________________ Page 1 of 5 SECOND MIDTERM EXAM ECEN 2120 - Lecture 1 November 8, 2002 Complete the top portion of the bubble sheet with your student ID number and your name. In the "1 2 3 4" columns, put a "0" in column 1 and your lab section number in columns 2, 3 and 4. If you want your grades included in a list of posted grades, please include a 6 alpha-numeric code in the space provided on the scan sheet. Print this code clearly. No obscene character sequence will be accepted. You must also sign your name in the space provided. Use a number 2 pencil to clearly select your answer. If you need more space to work a problem, use the back of an exam page. You have 50 minutes. Good luck! Questions 1-3. Consider an asynchronous serial communications system running at 9600 baud. This system is set-up to use 2 stop bits, 7 data bits and odd parity. The line is normally held at a logical "1". Assume that the character "R" (52H) is to be trans- mitted on the line. Question 1. (3 points) What is the value of the parity bit? (a) 0 (b) 1 (c) Not enough information. Question 2. (5 points) What is the "bit period" for this commu- nications set-up? (That is, how long does it take to transmit one bit?) (a) 104.17 msec. (b) 1.146 msec. (c) 104.17 usec. (d) 416.67 usec. (e) None of these. Question 3. (5 points) How many characters can be transmitted per second? (a) 9600 (b) 1371 (c) 1200 (d) 960 (e) 872 Question 4. (5 points) A system handling several devices wants to give equal service to each device. To achieve this goal, the system would probably use: (a) Priority Polling (b) A PIC (c) Round-robin polling (d) Mutual Exclusion (e) None of these. Question 5. (5 points) Which of the following lines of code would set PBIT in AL to zero, without modifying the rest of the bits. (a) OR al, mask PBIT (d) AND al, not mask PBIT (b) OR al, not mask PBIT (e) None of these. (c) AND al, mask PBIT Question 6. (5 points) A sequence of code that requires 24 machine cycles to execute is run on a 50MHz processor. How many seconds does it take to execute the code sequence? (a) 1200 sec. (b) 1.2 msec. (c) 480 usec. (d) 480 nsec. (e) None of these. Questions 7-11. In an 8086 system, a new interrupt handler is written to replace the interrupt handler associated with inter- rupt type 9. The name of this new interrupt handler is NewHan- dler and it is at offset 0564h with a code segment segment value of 2100h. Question 7. (5 points) At what location is the interrupt vector stored? (a) 2664h (b) 21564h (c) 36h (d) 24h (e) None of these. Question 8. (3 points) Invoking NewHandler is similar to per- forming a far jump. (a) True (b) False Question 9. (3 points) The code in NewHandler must set the I flag. (a) True (b) False Question 10. (3 points) When writing the code for NewHandler, the C calling conventions are used. (a) True (b) False Question 11. (5 points) If NewHandler is the interrupt service routine for a UART, which of the following registers would you expect to write before NewHandler could be invoked? (a) UART.IER (b) UART.LCR (c) PIC.OCW2 (d) a and b. (e) a and c. Question 12. (5 points) When using circular buffers, which of the following is not true? (a) An increment instruction, compare instruction and jump zero instruction can be used to update the pointers. (b) The buffer can be any length up to the size of a segment. (c) An increment instruction, IDIV instruction can be used to update the pointers. (d) The length of the buffer must be a power of 2. (e) The buffer may have multiple consumers. Question 13. (5 points) A DMA controller has been signaled by a driver to start its DMA transfer. Which of the following is not true? (a) The DMA controller may do cycle-stealing to perform the transfer. (b) The DMA controller will probably interrupt the CPU when fin- ished with the data transfer. (c) The DMA controller sends a signal on the HLDA to gain con- trol of the bus. (d) The DMA controller has a status register. (e) The DMA controller must become bus master. Question 14. (5 points) An assembly code sequence correctly implements a P operation on a binary semaphore named Flag. Which of the following statements is true? (a) The P operation increments Flag. (b) The P operation is executed before entering a critical sec- tion. (c) The semaphore is a 1 when a process is in the critical sec- tion. (d) The P operation supports mutual blocking. (e) b and c. Questions 15-17. Assume that you are dealing with the simple multi-processing system described in the text. Question 15. (3 points) A process waiting for I/O is in which of the following states? (a) Ready (b) Running (c) Blocked (d) None of these. Question 16. (3 points) The priority of a process is computed when it is in which of the following states? (a) Ready (b) Running (c) Blocked (d) None of these. Question 17. (3 points) When its time-slice is up, a process is put into which of the following states? (a) Ready (b) Running (c) Blocked (d) None of these. Question 18. (3 points) When discussing the RS 232 standard, it was pointed-out that only three signal lines are needed to make a connection between a computer and a terminal. Which of the fol- lowing would be used? (a) TD (b) CTS (c) DSR (d) DTR (e) a and d. Question 19. (3 points) Of the following registers in the UART, which is related to, or uses some of the RS 232 signal lines? (a) IIR (b) MSR (c) LCR (d) TXD (e) None of these. Question 20. (5 points) A system has four devices connected to it. Devices A and B are connected in a daisy chain to IRQ 4 of the PIC, with A closer to the PIC than B. Devices C and D are connected to IRQ 5 of the PIC, with C closer to the PIC. Assum- ing the interrupt service routines are properly written and everything is properly enabled, if all four devices simultane- ously want to interrupt the CPU, what is the order in which the devices will be serviced? (Priorities are 0 - highest, 7 - low- est) (a) D, C, B, A (b) B, A, D, C (c) C, D, A, B (d) A, B, C, D (e) None of these. Question 21. (5 points) Adding instructions to a piece of I/O code to "get the timing right" is similar to: (a) Busy-waiting (b) Polling (c) Entering a critical section (d) Looping (e) None of these. Question 22. (5 points) An assembly program is written to pro- duce short sequences of stereo sound. It uses two channels of a D-to-A converter. The D-to-A converter takes 16-bit input sam- ples to produce an analog voltage. The samples must be output at 44,000 Hz, to produce CD quality sound. At most, approximately how much time does the program have to output each sample? (a) 5.68 usec (b) 11.36 usec (c) 22.73 usec (d) 45.45 usec (e) Not enough information. Question 23. (8 points) Consider the following line of code: add Buffs,BX The variable Buffs is in the data segment at location 4531h. How many machine cycles does it take to execute this code? (a) 15 (b) 19 (c) 22 (d) 23 (e) 30 Some useful information. +---------------------------------------------------------------+ | Instruction Timing | +----------------------------+---------------+------------------+ | Instruction | No. of Cycles | No. of Transfers | +----+-----------------------+---------------+------------------+ |MOV | Register to register | 2 | 0 | | | Memory to register | 8+EA | 1 | | | Register to memory | 9+EA | 1 | | | Immediate to register | 4 | 0 | | | Immediate to memory | 10+EA | 1 | |ADD | Register to register | 3 | 0 | | | Memory to register | 9+EA | 1 | | | Register to memory | 16+EA | 2 | | | Immediate to register | 4 | 0 | | | Immediate to memory | 17+EA | 2 | +----+-----------------------+---------------+------------------+ +----------------------------------------------------+ | Effective Address Timing | +----------------------------------------------------+ | Addressing Mode No. of cycles | +----------------------------------------------------+ |Direct 6 | |Register Indirect 5 | | (BX),(DI),(SI) | |Register Relative 9 | | (BX),(BP),(DI),(SI) plus | | 8-bit or 16-bit displacement | |Based Indexed | | (BP)+(DI) or (BX)(SI) 7 | | (BP)+(SI) or (BX)(DI) 8 | |Based Indexed Relative | | (BP)+(DI)+Displ or (BX)(SI)+Displ 11 | | (BP)+(SI)+Displ or (BX)(DI)+Displ 12 | +----------------------------------------------------+ +----------------------------------------------------+ | Lab Sections | +-------------------------++-------------------------+ |Section Time ||Section Time | | 0011 8:00-9:50 TR || 0016 7:00-8:50 TR | | 0012 10:00-11:50 TR || 0022 10:00-11:50 MW | | 0013 12:00-1:50 TR || 0023 12:00-1:50 MW | | 0014 2:00-3:50 TR || 0024 4:00-5:50 MW | | 0015 4:00-5:50 TR || 0025 7:00-8:50 MW | +-------------------------++-------------------------+