SECOND EXAM ECEN 2120 - Lecture 1 November 5, 2004 This exam is closed book and closed notes. Complete the top portion of the bubble sheet with your student ID number and your name. Sign your name in the blank space at the bottom of the sheet. In the "1 2 3 4" columns, put a "0" in col- umn 1 and your lab section number in columns 2, 3 and 4. Please sign your name in the space provided under the Honor Code. Use a number 2 pencil to clearly select your answer. If you need more space to work a problem, use the back of an exam page. You have 50 minutes. Good Luck! Question 1. (5 points) In general, when using circular buffers, which of the following is not true? (a) An ADDQ instruction, compare instruction and BEQ instruction can be used to update the pointers. (b) The buffer may have multiple consumers. (c) The length of the buffer must be a power of 2. (d) An ADDQ instruction and DIVU instruction can be used to update the pointers. (e) A circular buffer is an implementation of a FIFO queue. Question 2. (5 points) In the 68000, to help processes share data, which of the following instructions is critical? (a) EXCH (b) CMPI (c) ADDQ (d) TAS (e) None of these. Question 3. (5 points) Which of the following is not true about reentrant code? (a) Reentrant code can be simultaneously executed by multiple processes. (b) A reentrant procedure must reinitialize itself at the begin- ning of each call to it. (c) One process must be able to call a reentrant procedure before the execution of the reentrant procedure due to a prior call has completed. (d) A reentrant procedure must consist of code which does not modify itself. (e) A reentrant procedure must store the data it will modify only in memory locations associated with the calling process. Question 4. (5 points) Which statement from the following is true? In DMA transfers: (a) Cycle stealing is implemented by interrupts. (b) Blocks are transferred by interrupts. (c) Interrupts must be disabled unless cycle stealing is imple- mented. (d) The DMA controller/device must be bus master during data transfers. (e) The DMA controller/device transfers data from an external device to the CPU. Question 5. (5 points) Consider the following macro definition: MyMacro macro A,B local base base set * L1 set *-base dc.w A L2 set *-base dc.l B endm When the this macro called with the string "X MyMacro C,D", what is the value of the label L2? (a) 0 (b) 2 (c) 4 (d) X+2 (e) Not enough information. Question 6. (3 points) What is the processor clock cycle time of a 2.5 GHz processor? (a) 0.4 nsec. (b) 4 nsec. (c) 400 micro-sec. (d) 400 nsec. (e) None of these. Question 7. (5 points) The value of MBIT is a mask that is set with an EQU. Which of the following lines of code would be used to "pull-out" the bits of D0 corresponding the 1's in MBIT? (a) AND #MBIT,D0 (c) BSET #MBIT,D0 (e) None of these. (b) AND MBIT,D0 (d) OR #MBIT,D0 Question 8. (5 points) When implementing the "V" operation on a semaphore, which of the following instructions would you expect to see in a sequence of code? (a) EXCH (b) CMPI (c) ADDQ (d) TAS (e) None of these. Questions 9-12. Consider an asynchronous serial communications system running at 4800 baud. This system is set-up to use 1 stop bit, 7 data bits and even parity. The line is normally held at a logical "1". Assume that the character "W" (57H) is to be trans- mitted on the line. Question 9. (3 points) What is the value of the parity bit? (a) 0 (b) 1 (c) Not enough information. Question 10. (5 points) What is the "bit period" for this commu- nications set-up? (That is, how long does it take to transmit one bit?) (a) 416.67 msec. (b) 2.083 msec. (c) 416.67 micro-sec. (d) 208.33 micro-sec. (e) None of these. Question 11. (5 points) At most, how many data items (charac- ters) can be transmitted per second? (a) 436 (b) 480 (c) 533 (d) 600 (e) 4800 Question 12. (5 points) The frame that represents the transmis- sion of the "W" is (from first bit sent on the left to last bit sent on the right, where the "P" represents the value of the par- ity bit): (a) 001010111P1 (b) 011101010P1 (c) 01010111P1 (d) 01110101P1 (e) 1110101P1 Question 13. (5 points) When discussing the RS 232 standard, which of the following signals is specifically there for use when connecting to Data Communications Equipment? (a) RD (b) DTR (c) FG (d) CTS (e) b and d are used. Question 14. (3 points) When using the UART, which of the fol- lowing would not be considered a control register: (a) IER (b) MSR (c) LCR (d) a and b (e) All are control registers. Question 15. (3 points) When using the UART, which of the fol- lowing would be considered a status register: (a) LSR (b) MCR (c) IER (d) RBR (e) b and c. Questions 16-17. Consider the MB5 68000 system that you have been using and an interrupt handler associated with the level 3 interrupt autovector. The name of this new interrupt handler is MyHandler and the linker has assigned it to be at location $106DC0. Question 16. (5 points) After the processor acknowledges an interrupt, the address of the first instruction the processor executes is located at which in which range of addresses given below? (a) $0-$3FF (c) $105000-$108000 (e) None of these. (b) $100000-$100200 (d) $1FF000-$1FFFFF Question 17. (3 points) When writing the code for MyHandler, the C calling conventions are used. (a) True (b) False Question 18. (3 points) When handling an interrupt from the UART, which of the following registers is repeatedly checked in the interrupt handler? (a) LSR (b) MSR (c) IER (d) IIR (e) None of these. Questions 19-21. Assume that you are dealing with the simple multi-processing system described in class. Question 19. (3 points) A process waiting for I/O is in which of the following states? (a) Ready (b) Running (c) Blocked (d) None of these. Question 20. (3 points) The priority of a process is computed when it is in which of the following states? (a) Ready (b) Running (c) Blocked (d) None of these. Question 21. (3 points) When its time-slice is up, a process is put into which of the following states? (a) Ready (b) Running (c) Blocked (d) None of these. Question 22. (3 points) When dealing with I/O devices in a sys- tem, which of the following schemes is "fair" from the point-of- view of whether a device will receive service? (a) Priority Polling (c) Daisy-chaining (b) A priority interrupt controller (d) Round-robin polling (e) c and d. Question 23. (5 points) A reset is similar to other processor exceptions. Which of the following statements is false regarding what happens when a reset occurs. (a) The processor starts executing code from the address stored at memory location 0. (b) The processor is put at priority level 7. (c) The processor saves the current value of SR on the stack. (d) The processor loads a value into the SP (or SSP). (e) b and d are false. Question 24. (5 points) Consider the following lines of code: btst.b #1,$5(A0) bne Label How many machine cycles does it take to execute this code? (a) 22 (b) 26 (c) 28 (d) 30 (e) Not enough information. Some useful information. Table D-1. Effective Address Calculation Times +-----------+---------------------+ |Addressing | Byte Long | | Mode | Word | +-----------+---------------------+ |Dn | 0 (0/0) 0 (0/0) | |An | 0 (0/0) 0 (0/0) | |(An) | 4 (1/0) 8 (2/0) | |(An)+ | 4 (1/0) 8 (2/0) | |-(An) | 6 (1/0) 10 (2/0) | |d(An) | 8 (2/0) 12 (3/0) | |d(An,X) | 10 (2/0) 14 (3/0) | |xxx.W | 8 (2/0) 12 (3/0) | |xxx.L | 12 (3/0) 16 (4/0) | |d(PC) | 8 (2/0) 12 (3/0) | |d(PC,X) | 10 (2/0) 14 (3/0) | |#xxx | 4 (1/0) 8 (2/0) | +-----------+---------------------+ Table D-8. Single Instruction Execution Times. +------------++---------+----------+ |Instruction ||Dynamic | Static | +------------++---------+----------+ | BTST ||4 (1/0)+ | 8 (2/0)+ | +------------++---------+----------+ + add effective address calculation time Table D-9. Conditional Instruction Execution Times. +------------+--------------+----------+-----------+ |Instruction | Displacement | Branch | Branch | | | | Taken | Not Taken | +------------+--------------+----------+-----------+ |Bcc | Byte | 10 (2/0) | 8 (1/0) | | | Word | 10 (2/0) | 12 (2/0) | +------------+--------------+----------+-----------+ |BRA | Byte | 10 (2/0) | - | | | Word | 10 (2/0) | - | +------------+--------------+----------+-----------+ |BSR | Byte | 18 (2/0) | - | | | Word | 18 (2/0) | - | +------------+--------------+----------+-----------+ |DBcc | CC true | - | 12 (2/0) | | | CC false | 10 (2/0) | 14 (3/0) | +------------+--------------+----------+-----------+