**Week 1****Mon. 1/11:**Read Section 1.5, Digital Representation of Information and watch the screencast Digital Representation of Numbers and Letters. If you don't have the book yet, here is a scan of Chapter 1**Wed. 1/13:**Watch the screencasts Decimal To Binary And Hexadecimal and Decimal Fraction to Binary Conversion.**Fri. 1/15:**Read Sections 2.1-2.4, Variables, Functions, Inversion, Truth Tables, Logic Gates and Networks and watch the screencasts Logic Functions: AND, OR, NOT and Analysis and Synthesis of Logic Networks. If you don't have the book yet, here is a scan of Chapter 2

**Week 2****Mon. 1/18:***** Martin Luther King Jr. Day *****Wed. 1/20:**Section 2.5, Boolean Algebra, Venn Diagrams. Related screencasts: Boolean Algebra I and Boolean Algebra II and Boolean Identity Proofs and Boolean Algebra Example.**Fri. 1/22:**Sections 2.6-2.7, Synthesis Using AND, OR, NOT Gates, NAND and NOR Logic Networks. Related screencasts: Synthesis Using AND, OR, NOT Gates and NAND, NOR, Logic Networks and NAND/NOR Only Example.

**Week 3****Mon. 1/25:**Section 2.8, Design Examples. Related screencast: Logic Building Block Examples.**Wed. 1/27:**Sections 2.9-2.10, Introduction to CAD Tools, Introduction to Verilog. Related screencasts: Introduction to Verilog Part 1 and Introduction to Verilog Part 2.

Download the Altera Software (Modelsim and Quartus II) and install it on your computer. It will be needed for the next homeworks. Also get the Terasic DE0 board (available at the e-store of the ECEE Department).**Fri. 1/29:**Section 2.11, Minimization and Karnaugh Maps. Related screencast: Minimization and Karnaugh Maps.

**Week 4****Mon. 2/1:**Section 2.12-2.13, Strategy for Minimization, Minimization of Product-of-Sums Forms. Related screencasts: Strategy for Minimization and Prime Implicants and More.**Wed. 2/3:**TBD Related screencasts: Intro to Verilog and ModelSim, Part1, Intro to Verilog and ModelSim, Part2, and Intro to Verilog and ModelSim, Part3. Watching these videos should also help you with Project 1.**Fri. 2/5********* Quiz 1 *******.

Closed book, closed notes, one sheet (8.5"x11", both sides, with your own notes) allowed. No calculators or cell phones. Covers Section 1.5, binary and hexadecimal representation of integers and fractions, and Chapter 2 in the book. For practice you can use some of the examples in Section 2.17 in the book, the problems from Chapter 2 which have a star next to them (solutions are at the end of the book), and the homework problems and their solutions.

**Week 5****Mon. 2/8:**Section 2.14, Incompletely Specified Functions. Related screencast: Incompletely Specified Functions.**Wed. 2/10:**Sections 2.15, 3.1, Multiple-Output Circuits, Positional Number Representation. Related screencast: Number Representation.**Fri. 2/12:**Section 3.2, Addition of Unsigned Numbers. Related screencast: Addition of Unsigned Numbers.

**Week 6****Mon. 2/15:**Section 3.3, Signed Numbers. Related screencast: Signed Numbers, Part 1.**Wed. 2/17:**Section 3.3, Signed Numbers. Related screencast: Signed Numbers, Part 2.**Fri. 2/19:**Section 3.4, Fast Adders. Related screencasts: Fast Adders, Part 1 and Fast Adders, Part 2.

**Week 7****Mon. 2/22:**Section 3.5 & Appendix A, Design of Arithmetic Circuits Using CAD Tools. Verilog and Quartus Demo. Related screencast: Arithmetic Circuits in Verilog, Part 1.**Wed. 2/24:**Section 3.5 & Appendix A, Half/Full Subtractors. Fast Adders. Design of Arithmetic Circuits Using CAD Tools. Click here for the Verilog Code Worksheet that we used in class. Related screencast: Arithmetic Circuits in Verilog, Part 2.**Fri. 2/26:**Section 3.7, Other Number Representations: Binary Coded Decimal (BCD). Related screencasts: BCD Adder in Verilog.

**Week 8****Wed. 2/29:**Section 3.7, Other Number Representations: IEEE Floating Point Numbers. Related screencasts: Other Number Representations.**Wed. 3/2:**Section 4.1, Multiplexers, Verilog Worksheet.**Fri. 3/4********* Quiz 2 *******.

Closed book, closed notes, one sheet (8.5"x11", both sides, with your own notes) allowed. No calculators or cell phones. Covers Section 1.5, binary and hexadecimal representation of integers and fractions, Chapter 2, Chapter 3 appendix A, and Verilog Design. For practice you can use some of the examples in Sections 2.17 and 3.8 in the book, the problems from Chapters 2 and 3 which have a star next to them (solutions are at the end of the book), and the homework problems and their solutions.

**Week 9****Mon. 3/7:**Appendix B.1, B.8, Transistor Switches, Practical Aspects.**Wed. 3/9:**Appendix B.3, B.8.8, CMOS Logic Gates, Transmission Gates. Related screencast: From Transistors to Gates.**Fri. 3/11:**Section 4.1, Multiplexers, Multiplexer Synthesis Using Shannon's Expansion. Related screencast: Multiplexers.

**Week 10****Mon. 3/14:**Sections 4.2, 4.3, Decoders, Encoders. Related screencasts: Decoders, and Encoders.**Wed. 3/16:**Section 4.6, Verilog for Combinational Circuits. Related screencast: Verilog for Combinational Circuits.**Fri. 3/18:**Section 4.6, Verilog for Combinational Circuits. Related screencast: Verilog for Combinational Circuits.

**Week 11****Mon. 3/21 - 3/25:***** Spring Break ***

**Week 12****Mon. 3/28:**Section 5.1, Basic Latch. Related screencast: Latches.**Wed. 3/30:**Sections 5.2-5.3, Gated SR Latch, Gated D Latch. Related screencast: Latches.**Fri. 4/1:**Sections 5.4-5.5, Edge-Triggered D Flip-Flops, T Flip-Flop. Related screencast: Edge-Triggered Flip-Flops.

**Week 13****Mon. 4/4:**Sections 5.6-5.8, JK Flip-Flop, Summary of Terminology, Registers. Related screencast: Different Types of Flip-Flops.**Wed. 4/6:**Section 5.9, Asynchronous Counters. Related screencast: Registers and Counters.**Fri. 4/8:********* Quiz 3 *******.

Closed book, closed notes, one sheet (8.5"x11", both sides, with your own notes) allowed. No calculators, cell phones, or smart watches. Covers Section 1.5, binary and hexadecimal representation of integers and fractions, Chapters 2, 3, 4, and Appendix B (only Sections B.1-B.3 and B.8) in the book. For practice you can use some of the examples in Sections 2.17, 3.8, 4.8, and B.12 in the book, the problems from Chapters 2, 3, 4, and Appendix B which have a star next to them (solutions are at the end of the book), and the homework problems and their solutions.

**Week 14****Mon. 4/11:**Section 5.9, Synchronous Counters. Related screencast: Synchronous Counters.**Wed. 4/13:**Sections 5.10-5.12, Reset Synchronization, Other Types of Counters, Using Storage Elements with CAD Tools. Related screencasts: Other Types of Counters, and Verilog for Storage Elements, Part 1, and Verilog for Storage Elements, Part 2.**Fri. 4/15:****TBD**.

**Week 15****Mon. 4/18:**Section 5.13, Using Verilog Constructs for Registers and Counters. Related screencast: Verilog for Registers and Counters.**Wed. 4/20:**Section 6.1, Basic Design Steps (Synchronous Sequential Circuits). Related screencast: FSM: Basic Design Steps, Part 1, and FSM: Basic Design Steps, Part 2,**Fri. 4/22:**Sections 6.2 and 6.3, State-Assignment Problem, Mealy State Model. Related screencasts: State Assignment Problem and Mealy State Model.

**Week 16****Mon. 4/25:**Sections 6.4 and 6.5, Design of Finite State Machines Using CAD Tools, Serial Adder Example. Related screencast: Finite State Machines in Verilog.**Wed. 4/27:**Sections 6.6 and 6.7, State Minimization, Design of a Counter Using the Sequential Circuit Approach. Related screencasts: State Minimization, Part 1 and State Minimization, Part 2 and Counter Design Using FSM Approach.**Fri. 4/29:**Sections 6.8, 6.9 and 6.10, FSM as an Arbiter Circuit, Analysis of Synchronous Sequential Circuits, Algorithmic State Machine (ASM) Charts. Related screencast: Algorithmic State Machine (ASM) Charts.

**Week 17****Mon. 5/2:**Final Exam 1:30 - 4:00 pm

©2012-2016, P. Mathys. Last revised: 1-10-16, AF.