This lab assignment is to get you familiar with the way that computers store data. To do this, we'll be introducing two new components: the latch, and the multiplexor. The functionality of the module should be as follows:
Required functionality:
You may use this module to simplify the use of the hex displays.
First, you'll want to make a custom 4-by-16 latch module. Build the following design:
lpm_latch can be found in c:/altera...->megafunctions->storage->lpm_latch. These LPM blocks are a little more complex than the lpm_constant block you worked with in lab 1, so this time when instanciating it, leave the Launch MegaWizard Plug-In checkbox checked. When the MegaWizard window pops up, leave the output file name as is, but make sure Verilog HDL is selected. Click Next. Change the bus width to 16, then click Finish twice.
After you've finished making that, create its' symbol file and then build the following design:
Again, you'll be implementing additional lpm modules. For the mux, be sure to right click and select flip vertical. For the lpm_constant, it may not look exactly the same as what's in the picture above.
Use this to configure your pins so you can show your TA.
For the report, submit your schematics and give the truth table for the sub-circuit that drives the G0 through G3 latch input signals. Also, please add a short paragraph about anything that could be improved with this experiment. Was there anything that you didn't quite understand, etc.