ECEN3100 - Digital Logic


Lab 3: Evaluating Adder Performance

2 lab period

Sign-off sheet

The goal of this lab assignment is to explore and understand adder performance within the context of FPGAs. We will be using lab 2 as a basis so after you've create your new project be sure to copy those files you used last time. Be sure to create new copies of your Lab 2 files in a new Lab 3 folder. The functionality of the module you'll be building should be as follows:

Pictoral representation of on-board resources utilized in this project

Required functionality:

You may use this module to simplify the use of the hex displays.

First, start off by creating a new project. Do not add any of your previous files yet. Create a new schematic file and save it as "schematic_adder". Add an lpm_add_sub module and configure it to be 4 bits wide, with just addition. Be sure to enable the carry input and output in the optional inputs and outputs page. Leave it unpipelined.

Pictoral representation of schematic_adder.bdf

Simulate it using a timing simulation (the default simulation type) and view the results when CIN goes from 0 to 1 and back when X is 15 and Y is 0. Make sure that CIN is high for at least 20nS. Also, you might want to change the length of the simulation by clicking Edit->End Time. 200nS is a good length. Also, you can change the grid size by clicking Edit->Grid Size. 50nS is a good size. How long does the correct value take to propagate to COUT when CIN goes from 0 to 1? You can find this by using the time measurement cursor. Try using the left and right cursor keys on your keyboard. How long does it take for the correct value to propagate to COUT when CIN returns to 0? Print your simulation results and attach them to your lab report.

Next, create a verilog HDL file and save it as "verilog_adder". Copy the following Verilog code into it. Set it to be the top level design file and simulate it using the same procedure that you used for the "schematic_adder" design.

module verilog_adder(CIN, X, Y, S, COUT);

input CIN;
input [15:0] X, Y;
output reg [15:0] S;
output reg COUT;
reg [16:0] C;
integer k;

	always @ (X or Y or CIN)
	begin
		C[0] = CIN;
		for (k=0; k<16; k=k+1)
		begin
			S[k] = X[k] ^ Y[k] ^ C[k];
			C[k+1] = (X[k]& Y[k]) | (X[k] & C[k]) | (Y[k] & C[k]);
		end
		COUT = C[16];
	end

endmodule

Next, modify the top block diagram file you copied in from lab 2 to look like what you see below. For the adder, use the same lpm_add_sub module as before, but make it 16-bit with selectable addition and subtraction and enable the output carry and overflow ports.

Use this file for your pin assignments.

Pictoral representation of lab3.bdf

In your report, how much slower was the verilog 16-bit adder compared to the 4-bit schematic adder? Why do you think that is?

Lab 3 - Part 2
Read the Signal Tap II tutorial Part 2 Tutorial and follow the instructions in Sections 1-4 to create and use an embedded logic analyzer on your DE2 board.

Use this file for your pin assignments.

For more practice and a little bit of extra credit, modify your top-level design to include an LPM multiplier module in parallel with the lpm_add_sub module and have the results displayed on HEX[3..0] when location 3 is selected. Note, you might want to configure it so that it restricts the number of bits output to 16. However, if you do so, it will be the upper 16 bit result, NOT the lower.