ECEN3100 - Digital Logic


Lab 5: Introduction to Verilog Design

4 lab periods

Now that you have a firm grasp of schematic design, the goal of this lab is to introduce you to the usage of Verilog design. Verilog is a programmatical approach to hardware design. In fact, it shares many aspects in common with programming languages you may already be familiar with, such as C++ or Java.

An introduction to Verilog

After you've completed the Verilog introduction, those of you working in pairs will complete lab assignment 5a. Those of you working alone will complete lab assignment 5b. It is not necessary to complete both assignments.

Assignment 5a
Assignment 5b

You may use this file for pin assignments.