The goal of this lab assignment is to explore and understand the implementation of flip-flops and other sequential logic devices, as well as see the difference between behavioral and sequential circuit descriptions. The functionality of the first part of this lab will be to implement both D and T flip-flops with a behavioral description in Verilog. The functionality of the second part of the lab will be to implement the JK flip-flop with a structural implementation, either in Verilog or schematic form.
You may use this module for the generation of the 0.5Hz clock.
Demonstrate that your flip-flops work to your TA using this pin assignments file.Be sure to get signed off with this sign-off sheet.