ECEN3100 - Digital Logic

Lab 7: Introduction to Sequential Logic

2 lab periods

The goal of this lab assignment is to explore and understand the implementation of flip-flops and other sequential logic devices. It will be divided into two parts. The functionality of the first part of this lab should be as follows:

Pictoral representation of on-board resources utilized in this project

Required functionality:

Within the FPGA you shall construct T, D, and JK type flip-flops in Verilog.
KEY[0] should connect to the T flip-flop's T input, and LEDG[0] should be its' Q output.
KEY[1] should connect to the D flip-flop's D input, and LEDG[2] should be its' Q output
KEY[2] should connect to the JK flip-flop's J input, KEY[3] should connect to its' K input, and LEDG[5] should be its' Q output.
Connected to all three should be an 0.5Hz clock. For ease of use connect it to LEDG[7], as well.

You may use this module for the generation of the 0.5Hz clock.

Demonstrate that your flip-flops work to your TA using this pin assignments file.

The second part of this lab explores the use of the extension board called D.O.U.G.L.E.. This board allows you to familiarize with discrete components. The functionality of the second part of this lab should be as follows:

The D.O.U.G.L.E. board should be connected to the DE2 board with a ribbon cable joining the two connectors labeled GPIO_0. (The name is the same on both boards. The DE2 board supplies power and ground to the daughterboard. The inputs and outputs are also controlled and examined on the DE2 board.
SW[0] should be connected to PIN_E26 and PIN_F24 of the GPIO_0 bank. Note that the signal names are the same on both sides of the ribbon connector. This makes your life easier. You will access these signals from the JP1B female connector of the daughterboard.
PIN_L25 of the GPIO_0 bank should be assigned to LEDG[0].
If you have never worked with breadboards, consult your TA before proceeding.
You should place one SN74LS00N chip on one of the breadboards of the D.O.U.G.L.E. board. The datasheet for this component is here. Your TA will give you parts and wires.
Connect PIN_E26 and PIN_F24 to the inputs of one of the NAND gates on the chip. Connect PIN_L25 to the output of that same gate. Finally connect the power and ground pins of the chip to the 5V and GND pins of the JP1B connector.

Compile your design to the DE2 board and demonstrate to your TA that LEDG[0] behaves like the output of an inverter controlled by SW[0]. Be sure to get signed off with this sign-off sheet.