ECEN3100 - Digital Logic


Lab 8: Moore and Mealy Machine Design

2 lab periods

The goal of this lab assignment is to build three finite state machines. The functionality of your design should be as follows:

Pictoral representation of on-board resources utilized in this project

Required functionality:

  1. Within the FPGA you shall first construct a Moore-type state machine.
  2. Next, you will add a Moore-type state machine of your own design with at least 5 states.
  3. Finally, you will add your 5-state state machine again as an equivalent Mealy-type.

Demonstrate that your state machines work to your TA using this pin assignments file. In your lab writeup, include printouts of the RTL Viewer output, the State Machine Viewer output (for all state machines that remain -- if any are missing, explain why), and as much of the Technology Map Viewer output that you can fit on a single page of paper. Each of these can be found in the Tools->Netlist Viewers menu.

Be sure to get signed off with this sign-off sheet.