For wirewrap projects in Capstone, we use the Xilinx Spartan XCS10 FPGA. The exact part designator is xcs10-3pc84. This is a part in an 84-pin PLCC package, and we have adaptors to provide wirewrap pins. FPGAs don't have non-volatile storage for their programming, so they must be reprogrammed after every power cycle. To achieve this, we store the programming on a Xilinx 18v256 serial EEPROM, also in a PLCC package. Downloading the program to the EEPROM is done in-circuit, via a JTAG programming cable.

For wiring and hardware specifics, refer to the Xilinx technical documentation, available in the lab or online. Chapters on the Spartan and on the 18vX chips both have good schematics for connection. In short, the EEPROM and FPGA should be connected in a JTAG chain, and there should also be a DO/DI connection between the two chips. The Xilinx Data Book 2000 contains several useful sections that you should review before continuing. Chapter 4, starting on page 4-61, describes the Spartan FPGA that we are using. Chapter 5 describes the use of FPGA's with a configuration PROM. Figure 5 on page 5-9 shows the wiring connections for multiple PROM's and FPGA's, which you can adapt for your needs.

For the Spartan FPGA, you must use Xilinx ISE 4, available on all of the workstations. To begin working with ISE, start the Project Navigator. Create a new project by going to the File → New Project. Give the project a name, and set the location to a directory either on your Z: drive or in your group's shared directory. The rest of the options are dropdowns, and should be selected as follows. The Device Family should be Spartan, and the Device is xcs10-3pc84. For Design Flow, you may choose either Synplify Pro VHDL or Synplify Pro Verilog, depending on your language of choice. If you plan to use schematics to create your design, then this choice is arbitrary.

The Xilinx ISE design manager does not directly support using schematics with the Spartan FPGA family. It can be done though, and this section will tell you how.

To start, you should have three links on your desktop for supporting schematic entry: "Schematic Editor", "Convert SCH to VHDL", and "Convert SCH to Verilog". If you don't have these links, please ask a TA to configure your system accordingly.

Open Schematic Editor using the link on the desktop. Before you create a new schematic, first go to the menu Edit → Preferences. There is a drop-down box for Default Device Family - change that to 'spartan'. Now you may use File → New to create a new schematic. Enter the schematic as normal. Note that you do not need to place IO buffers on inputs/outputs - the process we're using will automatically insert those as needed. Just add an I/O marker with the name of the signal and the appropriate direction. When you are finished with your design, save it into your project directory.

The next step for your schematic is to convert it either to VHDL or to Verilog, depending on the design flow you chose for your project. Use explorer to browse to your project directory. Find the saved schematic (with a .sch extension), and drag it onto the appropriate "Convert SCH to ..." icon. You should get a new .v or .vhd file in your project directory.

Once you have added the file to your project, any changes wll automatically be detected. If you change your schematic, just run it through the convert script again, and then project navigator should pick up the change.

The "Sources in Project" pane shows all of the files that have been added to your project. To create a new source file, just right clikc on the pane and choose New Source. The type should be either a VHDL or Verilog Module. The rest of the dialog will ask you about the ports you want in the module - you can skip this if you want and add them manually. Note that for VHDL files, you should include the libraries for the spartan part, as follows:

LIBRARY xc4000;
USE xc4000.components.ALL;

To add an existing source file, just right-click the pane and choose Add Source. Select your file and it will be brought into the project. You will want to do this if you have written your code elsewhere, or if you are importing the converted code from a schematic.

The "Processes for Current Source" pane shows the actions you can take for any given source file. The project navigator automatically keeps track of which processes are up to date, so if you try to start a process that depends on another process, it will run the dependencies first. The entries with the circle-arrows icon are project navigator processes. The entries with an empty box icon are external applications. The entries with a page icon are report files. You can start any process by double clicking its entry.

If you do not specify any pin constraints for your design, the mapper will determine on its own what is the best pin for each I/O signal. The report that specifies the pin locations is under Implement Design → Place & Route → Pad Report. The problem is that the best place may be different each time you run it, and you can't easily rewire your circuit every time to match! The solution is to lock the I/O signals to certain pins, by back-annotating the choices that the mapper made. Do this by selecting the Implement Design → Place & Route → Back-annotate Pin Locations process. After that has completed, you can edit the constraints file to make any changes needed. The editor can be reached in the process pane under Design Entry Utilities → User Constraints → Edit Implementation Constraints File.

The Spartan FPGA has what is perhaps unintuitive behavior for boundary scan (JTAG) operation. On an unprogrammed Spartan, the boundary scan operates on a very minimal subset of the full JTAG specification, intended only for reading its configuration from an EEPROM. Once the Spartan has been configured, the default action is to release all of the JTAG pins to be general I/O pins. Thus, once the device is configured, it will no longer respond on the JTAG chain. Because of the way JTAG works, if one device is not responding and passing the TDI/TDO chain through, then none of the devices on the JTAG chain can be seen by the host computer. In this scenario, you will not even be able to program the EEPROM with a new configuration.

The solution to this is to instantiate a BSCAN block in your design. Then the Spartan will behave as a proper boundary scan device, and you will be able to perform the usual operations on the chain, like programming the EEPROM. All that needs to be done is create the block and make connections to the TDI, TMS, TCK, and TDO pins. An example of what this should look like in a schematic is shown to the right, and examples of Verilog and VHDL skeleton modules are shown below. The highlighted portions are the essential parts that you should add to your own Verilog/VHDL designs.

If you accidentally programmed your EEPROM without including a BSCAN block in your design, then it may appear that you cannot program your device anymore. The iMPACT programmer will likely give a general complaint about a hardware configuration error. You can hold-off the FPGA from programming by pulling the /INIT pin down to a logic zero (ground). Once this is done, power-cycle the board, and iMPACT should now be able to identify the chain. Don't forget to release the /INIT pin after you have corrected the situation.

Verilog instantiation of BSCAN
module bnd_scan ( );
    wire TDI_NET, TMS_NET, TCK_NET, TDO_NET;
    BSCAN U1 (.TDO(TDO_NET), .TDI(TDI_NET),
              .TMS(TMS_NET), .TCK(TCK_NET));
    TDI U2 (.I(TDI_NET));
    TCK U3 (.I(TCK_NET));
    TMS U4 (.I(TMS_NET));
    TDO U5 (.O(TDO_NET));
endmodule


VHDL instantiation of BSCAN
LIBRARY xc4000;
USE xc4000.components.ALL;
ENTITY bnd_scan IS
    port (
         );
END bnd_scan;
ARCHITECTURE implementation OF bnd_scan IS
    signal TCK_NET  : STD_LOGIC;
    signal TDI_NET  : STD_LOGIC;
    signal TMS_NET  : STD_LOGIC;
    signal TDO_NET  : STD_LOGIC;
BEGIN 
    U1: BSCAN port map (TDO => TDO_NET, TDI => TDI_NET,
                        TMS => TMS_NET, TCK => TCK_NET,
                        TDO1 => open,   TDO2 => open);
    U2: TDI port map (I => TDI_NET);
    U3: TCK port map (I => TCK_NET);
    U4: TMS port map (I => TMS_NET);
    U5: TDO port map (O => TDO_NET);
END implementation;

The first step to program your FPGA is to run the process labelled Generate Programming File. Then, underneath that process, there are two utilities we need for programming. First, run the Generate PROM File process. This will bring up the PROM File Formatter with your .bit file already entered. Go to File → PROM Properties, and check the settings on the Format tab. The PROM File Format should be EXORmacs. Type is Serial, and PROM File is Single PROM. Under PROM Device, clear the Automatic Selection box, and in the dropdown select the XC18V256. You can click the Save Defaults button so you don't have to fix this every time, then close the properties window. Save the setup (.pdr) into your project directory, and then go to File → Create PROM. You can now close the PROM File Formatter.

Next comes the actual device programming. Before you start this, you should make sure that the JTAG programming cable is connected to you computer and your FPGA board, and the power to your board is on. Right-click on Configure Device (iMPACT) and go to Properties. Change the Configuration Mode to Boundary Scan. Then close the properties and double-click the process to start iMPACT. Make sure you are on the Boundary Scan tab. Then right-click an empty area and choose Initialize Chain. The diagram should now show the xc18v256 EEPROM, and an UNKNOWN device that is your FPGA. For the configuration file of the EEPROM, change the file type to EXO Files and select the .exo in your project directory. It will also ask if you have a BIT file or BSDL file for the FPGA - say Yes, and choose the .bit file in your project directory. You can now program the EEPROM by right-clicking it. Now when you power-cycle your board, the FPGA should read its configuration from the EEPROM, and set its DONE pin high.

If you get an error when trying to Initialize Chain, make sure that the power is on for both the FPGA (5V) and the EEPROM (3.3V). Check the connections for all the JTAG signals, especially the TDI/TDO loop. If all looks good, may you have a problem with the BSCAN on the spartan - see The importance of BSCAN above for details.