Importing Synthesized Verilog into Cadence

This tutorial will take you through the steps to import your synthesized verilog into cadence

1. From the main Cadence CIW window: File --> Import --> Verilog ...
2. Essentially, leave all defaults, and enter in your library name and CORLIB as the reference lib and add vdd! and gnd! to the Power Net Name and Ground Net Name



3. For further details, see the directions on the Importing Verilog into DFII website (starting on pg 14)
4. This creates a schematic view (and would also create symbol and functional views if they did not already exist). The schematic is based on the synthesized verilog using the CORELIB standard cells. You can now run simulations of the synthesized code as either verilog (using the msps view for all CORELIB parts) or transistor level analog (by using cmos_sch view for CORELIB parts). As usual, you will need a simulation setup schematic and a config view for mixed-signal simulation.