Cadence Design Tools

Cadence Tools  |  ECEN 5837 (Mixed-Signal IC Design)

AMS C35 Inverter Example

Part I: Schematic Entry & Simulation

This tutorial introduces Cadence schematic capture (Virtuoso Schematic Capture) and spice simulation (Affirma Design Environment, Spectre Simulator, and Waveform Viewer) using the AMS C35 process HIT-Kit.

1.      Open Cadence with the AMS C35 HIT-Kit and create a library ams_5007 for this course (if you have not already done so) as described in Using the AMS C35 process HIT-Kit.

2.      From the Library Manager, create a new “cell” for the inverter in your ams_5007 library:

a.      Left click on ams_5007 in the Library column

b.      Left click in the blank box under the Cell column

c.      Type in a name for your new cell: inv1 then hit enter

d.     

This pops up a Create New File window. Confirm the correct library, cell name: inv1, view name: schematic, tool: Composer-Schematic, select OK. This brings up the schematic editor for the new cell inv1.

3.      Add components for simulation:

a.     

In schematic editor, select  File à Add à Instance  (or keyboard shortcut  i  or click instance icon on left)

                                                   i.      You can type in library and cell directly if you know them. In this case, click  Browse

                                                 ii.      From library browser, select  PRIMLIB à pmos4 à symbol  (do not select close)

                                                iii.      Move mouse back to schematic window and you will see a p-type mosfet symbol moving with your mouse. Left click to place an instance of pmos4 (you could continue to left click to add additional instances).

a.      Go back to the Add Instance window (or hit shortcut  i  if you closed the window), replace Cell entry with  nmos4

                                                   i.      Move back to schematic window again to place instance of nmos4.

b.     
Following the above procedures, add instances of the global symbols vdd and gnd from the analogLib library (Library: analogLib, Cell: vdd, View: symbol), resulting in a schematic similar to above. NOTE: vdd and gnd are simply an example of using global symbols. We will have to connect a power supply between these nodes at some point in the hierarchy prior to simulation.

4.     

Wire the components by either placing the mouse over the nodes and dragging the left mouse button, or use the keyboard shortcut  w  then left-click to start and stop wiring, or click the  wire (narrow)  button on the left.  To stop wiring, press ESC.  To undo wiring, use the shortcut  u  .  Complete wiring as shown (don’t forget the body connections on the transistors).

c.      Note: you may appreciate the following shortcuts: f  (fit in window),  z  (zoom with left mouse clicks),  [  ]  (zoom in & out),  arrow keys  (move around screen),  9  (with mouse over wire, highlights all connections).

d.      Label the wires by placing the mouse in the schematic window, type the shortcut  l  (for label), enter name  in  Add Wire Name window, hit TAB key, then click on the input node in the schematic window. Repeat for label  out.

5.      Edit the component parameters:

e.      With the mouse in the schematic editor window, type the shortcut  q  (Edit à Properties à Objects…) then left click on the nmos4 device (MN0 above). In this menu, Width is the total channel width (all parallel devices, calculated automatically if Width Stripe is a number), Width Stripe is the channel width of a single device, Length is the channel length of all devices, and Number of Gates is the number of parallel devices. Define the Width Stripe and Width as a variable  Wn  to give some flexibility in the simulation, Length: leave at 0.35u, 1 gate, leave all other entries as default (see below). Note that you could have entered these details in the window when you first placed the device in the schematic as well. Repeat for the pmos4 device, with a Width Stripe: 3u, Length: 0.35u, Gates: 1.


 


6.      Create a Symbol: from here, you could add test voltage sources and run a simulation. However, it is better practice to create a symbol and a hierarchical design with the simulation setup in a separate Cell View. This allows the details of your design (schematic, layout, etc) to be independent of any simulation setups, which makes the design more portable and will be very useful later for layout verification (LVS).

a.      Create input & output pins: Pins are used in symbols and hierarchical designs to define the I/O of a cell. Within the schematic view, hit the hotkey  p  (or Pin icon on left or Add à Pin ...) , type in Pin Name: in, Direction: input, hit the Tab key, then place the input pin in your schematic; repeat for the Pin Name: out, Direction: output. Note: the input/output designations have no electrical meaning. They only determine the appearance in your schematic.


 


b.      Save your schematic: click the “Check and Save” icon in the upper left. Your CIW window should note that the schematic was saved with no errors or warnings. Any errors or warnings will be highlighted in your schematic and should be fixed before moving on.

c.      Create the symbol by selecting from the menu: Design à Create Cellview à From Cellview...

d.      Confirm in the pop-up window the Library, Cell Name, and From View Name: schematic, To View Name: symbol, select OK.

e.      The Symbol Generation Options window pops up. The pin specifications (left, right, top, bottom) can be adjusted if needed. This just determines how the auto-generated symbol looks. Select OK.

f.        An auto-generated symbol is then displayed as a box with the preset I/O. You can click the Save icon on the left to accept this symbol and move on, or you can use the drawing icons on the left to change the symbol if you desire (e.g. create a more traditional triangle for the inverter). We will leave the rectangle for now.

g.      After saving your symbol, exit out of the symbol viewer and exit from your schematic editor (Window --> Close).

7.      Create a test setup schematic for simulation.

a.      From the Library Manager, create a new schematic Cell: inv1_sim (using the same procedure as before for Cell: inv)

b.      Add the following instances (hotkey i ) from the analogLib Library for the simulation setup: vdd, gnd, vdc (with dc voltage 3.3V), and vpulse (with dc voltage 0V, v1: 0V, v2: 3.3V, rise & fall time: 10ns, pulse width: 5us, period: 10us)

c.      Add an instance of your inverter from your ams_5007 library: inv1. Wire your schematic as shown below. Note: the out pin is not needed. However, it is useful to have a wire at the output for selecting in the simulation, and a wire with only a single connection will give you warnings when you Check and Save.

d.      Be sure to hit the Check and Save icon on the left when you are complete and correct any errors.


 


8.      Perform a dc sweep simulation:

a.      Start the simulator: From schematic editor select  Tools à Analog Environment , the Affirma Analog design environment will come up, then setup the simulation:

b.      With the AMS HIT-Kit, the device models are already configured for the simulation. To view the model locations, select  Setup à Model Libraries …  Note that there are models for the cmos devices (cmos53.scs), as well as resistors, capacitors, and bipolar devices. There is also a setup library for Monte Carlo statistical simulations (mcparams.scs) that we will use later. These models use the section ...tm, which is for typical mean simulations. We will also later show how to use corner model simulations at the worst case corners of the process (instead of typical parameters). Select Cancel to close the window without changes.

c.      Add a design variable: We set the width of the nmos4 device to a variable Wn to demonstrate how to use design variables. Define the variable for the simulator by selecting Variables à Edit... (or clicking the x, y, z, icon). Enter Name: Wn, Value: 1.5u à Add à OK.


 


d.      Setup the analysis type: select Analyses à Choose … (or use icons on right)

                                                   i.      Select  dc  analysis, sweep  Component Parameter ,   left click on  Select Component , place mouse back into schematic window and left click on the pulse voltage source vpulse, in pop-up menu choose first item DC voltage, place mouse back into Choose Analysis window, enter sweep range: Start: 0 , Stop:  3.3 .  Should look like below:


 


                                                 ii.      Note: this shows how to sweep component parameters directly, without defining formal variables. You could also have defined the dc voltage as a variable (similar to Wn in the nmos4), then selected Design Variable in the Sweep Variable window. Click  OK.

f.        Setup outputs to plot: In the schematic window, descend into your inverter instance by placing your mouse over the inv1 instance, then hitting the middle mouse button, and selecting Descent Edit ... (or hitting the E hot key), then hit OK for descend into the View: schematic. This is how you move up & down the hierarchy (to return to the top, use the hot-key Ctrl-e), and allows you to select node voltages or device currents from anywhere in your design for probing in simulation. In this case, we will select probes from the top view, so return to the top view (Ctrl-e). Select  Outputs à To Be Plotted … à Select on Schematic

                                                   i.      Place mouse in schematic window, then left click on in and out wires (should change color as you select them which will match the colors in the simulation plots), then left click on the top terminal of your 3.3V vdc power supply (this will create a circle around that terminal, designating a probe on the current into the source). Then hit ESC key. Return to Affirma simulation window and the outputs should be setup as below.

                                                 ii.      This setup will cause plots of the desired signals to pop up immediately after the simulation. You can also just run the simulation then select the signals to plot after the simulation. Note: the default for Cadence is to save all node voltages and no currents for use in the Waveform Viewer. To make all voltages and currents available, select Outputs à Save All..., then depress the all box for power signals and device currents. The drawback is a slower simulation for very large circuits (keep this in mind for the last few HWs and your final project).


 


9.     

Run the simulation: Select  Simulation à Netlist and Run  (or use icon on right)

g.      A message file will pop up (ignore most warnings, resolve any errors), and messages will also be in the CIW window.

h.      The waveform window will also pop up with the outputs in, out, and the current in the power supply plotted.

i.         NOTE: as you go back & forth between the schematic & simulator, you must click “Check and Save” in the schematic window each time. If your simulator fails before starting, going back to save your design is the first debugging step.

j.         The default is for all waveforms to be on the same y-axis. To split the waveforms to separate axis, click on the Switch Axis Mode icon on the left in the Waveform Window. If you double left click on a waveform, you can setup the color and appearance and setup the y-axis (for multiple y-axes on a single plot) and the Strip (separate rows of plots in the window). Change the two voltages to have the same Strip number 1.

k.       Under Axis à Options ... You can select to show the grid. Marker icons on the left A and B allow you to set x-y markers on the waveforms.

10.  Run a transient simulation by following a similar process to above with a simulation type of: tran with a reasonable stop time (e.g. 40us). You could also set the DC bias of the input voltage in the transition region where both devices are in the active mode, set the ac component of the input source to 1, and run an AC simulation to plot the frequency response of the inverter.