Cadence Design Tools
Software | ECEN 5837 (Mixed-Signal IC Design)

AMS C35 Inverter Example
Part III: Layout and Verification

This tutorial builds on Part I to introduce custom layout of the inverter and layout verification (compliance with layout design rules, or design-rule-check (DRC), and confirmation that layout matches the schematic, or layout-vs-schematic (LVS) check).

  1. Inverter Layout: to begin the layout, we need to create a layout view of the design.
    1. From the Library Manager, select Library: ams_5007, Cell: inv1, then from the menu, select: File --> New --> Cellview...
    2. In the pop-up, change the tool to Virtuoso. You should see the View Name change to layout. Select OK.

    3. This brings up two windows: a blank layout window (similar to the schematic window) and an “LSW” window with all of the available layout layers (with appearance, name, and dg (drawing) or pn (pin) designation). We will primarily use only the first 21 layers, from NTUB to PAD. Note that there is a glitch in Cadence so that you cannot close the LSW window without exiting Cadence completely. The first few layers include:
      1. NTUB: n-well for pmos devices;
      2. DIFF: used for drawing any diffusion (n or p type for transistors and for substrate and well contact);
      3. NPLUS: designates any diffusion within the box to be n-type diffusion
      4. PPLUS: designates any diffusion within the box to be p-type diffusion
      5. MIDOX: designates a thick oxide (not used for now)
      6. HRES: designates poly within box to be of high resistance type (not used for now)
      7. POLY1: 1st layer poly-silicon, used for transistor gates
      8. POLY2: 2nd layer poly-silicon (not used for now)
      9. CONT: designates contact from diffusion to MET1
      10. MET1-4: four metal layers; dg and pn are the same but appear differently on the screen (dg for standard drawing and pn for pins)
      11. VIA1: metal via between MET1 and MET2 (similar for VIA2-3)
      12. PAD: designates area for bonding pads where protection silicon-dioxide layer will be etched away (used only in final project
    4. From this point, proper layout is somewhat painful until you learn the most common layout rules. It is best if you spend some time reading the layout rules from AMS Design Documents, C35 design rules.
    5. The best starting point is to quickly sketch a top-view of the desired layout, making decisions on whether the poly gates will be vertical or horizontal, where metal contacts will be placed and how metal will be routed for I/O and power supplies, and how or if you will be paralleling any devices. Once these decisions have been made, it is important to be consistent with device orientation and layout when matching is critical. Note that if you do parallel devices, you should go back and change the schematic to match. There is a tool in cadence for auto-generation of parameterized cells (or p-cells) such as mosfets, resistors and capacitors, that will auto-create devices with specified dimensions, contacts, etc. This function has been disabled for now so you will have experience designing devices manually, which is generally necessary for complex analog circuitry. NOTE: ignore warnings that the pcell license is not enabled.
    6. Once you have a general sketch of the layout (on paper or in your mind), you begin by selecting a layout layer from the LSW window, then a drawing shape from the icons on the left side of the layout window. Here we will draw the inverter with the gates vertical, starting with the gate for the pmos.
      1. The process allows you to layout on a 0.01u grid. However this is generally more trouble than it is worth, and all layout rules are in multiples of 0.05u. Change the grid by selecting from the layout menu: Options --> Display ... (or hotkey e), then changing the X Snap & Y Snap spacing to 0.05 (which is in micron). To set these as your default values: at the bottom of the Display window select file and click ‘Save To’.  This will write all your current setting values to a file in you root directory.  So every time Virtuoso is loaded these values will be loaded.  (Note: When in Schematic options =>save defaults; will save all your currents setting values for schematic). This is the grid your mouse operates on (the Minor & Major spacing designates the visible grid). In this menu, you can also change how you are able to move blocks when creating new or editing (Snap Modes): orthogonal, diagonal, vertical, horizontal, or any angle. The last option is the easiest to work with, but makes it easy to make alignment mistakes. The more limiting options force alignment, but can be frustrating when moving blocks around your layout. Another useful option is in Options --> Layout Editor ... (hotkey E), where you can click to enable/disable “gravity” control, which forces your mouse to block edges or labels when it is close. The hotkey “g” also turns gravity on and off.

      2. To draw the gate, note the layout rules under the heading 4.1.3 POLY1. To shrink the tutorial layout we will use a 5u x 0.35u pmos device (and make the same change to the schematic). We need a 0.35u (for length) by 5u (width) + the required poly overhang (rule PO.O.1 = 0.4u) on each side of the transistor, plus some distance for the poly contact. Start with a 0.35u x 7u block by:
      3. Select POLY1 from the LSW window, Rectangle icon in the layout window (left side, you may need to increase the window size, or use hotkey r, or select from the Create menu), then left-click to create the poly rectangle. Monitor the dX and dY values on the top of the window to help with the size.
      4. Now add diffusion for the source & drain regions. This is done by drawing DIFF directly across the channel (it is understood that this creates a transistor and diffusion will not be place in the channel region, and the oxide under the poly will be reduced to the thin gate oxide in the channel region). The DIFF should be exactly 5u (for device width) and long enough for the source & drain contacts. Note under 4.1.6 CONT, rule CO.W.1 shows that contacts must be a fixed 0.4u wide, and CO.C.1 shows 0.3u min spacing to the channel and CO.E.1 shows min DIFF enclosure of the contact is 0.15u. A first estimate on the DIFF length is 2.1u.
      5. Select DIFF, Rectangle, create 5u x 2.1u box for the pmos device. Use the hotkey z for zoom, arrow keys for panning the window, hotkey k for a ruler, and f for fit design in window. Also, hotkey m is useful for moving the DIFF box and centering over the gate poly, F6 for redrawing.
      6. Follow similar procedures to draw in 0.4u x 0.4u CONT (contacts) up and down the diffusion spaced by 0.4u and add a contact for the poly gate (note that the POLY1 must enclose CONT by 0.2u on each side, rule CO.E.2). For the CONT in diffusion, it will be useful to use the hotkey c for copy. To auto-generate an array, place the mouse over a single 0.4u x 0.4u CONT, hit c, then hit F3, fill in the pop-up for 5 rows, 1 column, TAB, the pull the mouse down, place the first copy with left-click, then place the 2nd copy with 0.4u separation. You will see all 5 in the string get placed. Again, the ruler k and move m will be useful (and K (shift-k) for remove rulers). Another useful command is stretch (hotkey s). Place the mouse over the edge of one side of a rectangle, hit s, then move the mouse to stretch a rectangle (e.g. DIFF or POLY1) in that direction. Finally, you can use default contacts from the library (with min dimensions). In the layout window, use the hotkey i for insert --> Browse --> TECH_C35B4 --> P1_C --> symbolic --> then place into your layout. This is a standard POLY1 contact (to metal 1). It shows as a hierarchical box. To show all layers in the hierarchy, hit the hotkey F (shift-f). The result with DIFF, POLY1 and CONT is shown below.

      7. Now, we have to designate the DIFF as p-type using the PPLUS layer and add n-well contacts. For the inverter, the n-well is tied to the pmos source, so we can abut the n-diffusion for the n-well contacts up to the pmos source. The source can be either side at this point, let’s use the left side. Add an additional column of DIFF abutted to the pmos source and copy your contacts over. Next, add a PPLUS rectangle to designate the DIFF of the pmos as p-type and NPLUS over the DIFF and contacts you just added to designate as n-type for the NWELL contacts. Now, draw in the n-well for the device (NTUB, must enclose PDIFF by 1.2u, rule OD.C.4, and NDIFF by 0.2u, rule OD.C.1). Again, whether DIFF is NDIFF or PDIFF is determined by the NPLUS or PPLUS designation. Finally, draw metal one over your source & drain contacts and gate contact. The complete pmos device is shown below:

      8. To check your design for layout rule violations, perform a design-rule-check (DRC).
        1. Assura --> Run DRC...  if you leave all defaults and click OK, you will get many warnings and errors, some due to real rule violations you may have and others due to complete layout constraints that are not relevant at this time (you can try this by clicking OK). To limit messages to only relevant ones
          1. select Set Switches in the DRC window --> select (with shift key):
          2. no_coverage & no_generated_layers : you can always use this, only applies to final layout
          3. no_erc & no_info: this can be used at first to focus only on design rule violations
        2. Run DRC with these three switches set. (if needed: click ok to overwrite, click yes to stop viewing current job) Then click yes to view results. In the new window that pops up click the AV button to outline all the errors (if any) (A window Redraw may be needed for the outlines to show up Window => Redraw in the layout window). To zoom inand place and X on the error select the error type you wish to view in the left box then click the button to scroll through the available errors. (use shift-z to zoom out).
        3. Correct all of your violations so there are no errors. Again, the stretch s command and ruler k are useful. It is also useful to re-create some shapes using the Polygon (hotkey P), since each time you click your mouse the dX and dY reference is reset, making it easy to set each dimension according to the rules.
        4. Re-run DRC with only the no_coverage and no_generated_layers switch set. This should give you three warnings:

        5. Floating gate is due to no pin on the gate or other connection; BAD_SUBSTR: is due to a lack of substrate contacts; and hot nwell is a term for n-wells that are not tied to vdd!. We can remove the first and last errors by assigning labels to vdd!, in and out. The No Stamped Connection error will remain until we complete the nmos device with a substrate contact. In general, your layouts should be “DRC Clean” with only the no_coverage & no_generated_layers switch's set, meaning no errors. To delete error markers: In the Error Layer Window (ELW) click the NV button.
      9. Add labels (the same as pins in schematic) by selecting: Create --> label from the menu or use the l hotkey. Change the height to 0.5 (so labels are not so large). Write in terminal Label: vdd!, TAB, then move your mouse into the layout window and place the vdd! label so that the + in the middle of the label is on the MET1 of your pmos source. Repeat for terminals: in (input) and out (output). Now select all of the labels by holding the shift key and clicking on each label (a dotted box will pop up around the object you are about to select). Click the properties button or the Q hot key. In the Edit Label Properties window check the Common button and select Layer: PIN M1. Hit the ok button to return. The design with labels is shown below.

    7. Repeat the same procedure to draw the nmos. Use dimensions of 2.5u x 0.35u (don’t forget to change the schematic as well). Again, draw the POLY1 gate, DIFF, source & drain contacts (CONT), DIFF and CONT for the substrate contact, then NPLUS over DIFF in nmos source & drain and PPLUS for DIFF in substrate contact. Add a pin for the nmos source and substrate contact labeled: gnd!.
      1. Fix all errors until your layout is DRC Clean with only the no_coverage switch (see below).

  2. Layout verification: finally, we need to verify that the layout matches the schematic, and later use extracted views with parasitic elements for more accurate simulation.
    1. Adjust device sizes your schematic to match the layout you just completed (if not done already).
    2. In the layout window: Assura=>Run LVS... Leave all defaults, OK.

    3. If you did every thing right a window should pop up stating that "Schematic and Layout Match." It will then ask you if you want to see the results, click Yes.
    4. It will open your schematic window (if not already open) and the LVS Debug window. If every thing is correct it will say Layout and Schematic Matched. If not the left windows shows which cells don't match (for us they should say the same thing). The right window (Summary) will tell you the specific problems and if you highlight the error and click Open Tool... a new window pops up and tells you the specific mismatches.

    5. Now you can cross-probe between the schematic and layout from the LVS Debug window. Select Tools => Probe. In the Assura Probing window click Add Probe and click a net in either the Layout or Schematic window. The net you click on should become highlighted. The same net in the opposite window should also become highlighted the same color.

      The following picture shows the net "out" being probed

    6. After you get a "clean LVS" you can extract the design. To extract open Assura=>Run RCX... choose the Extraction tab and for the Ref Node enter gnd!. As shown below. Leave the rest as default and click ok. Click yes to overwrite and it should complete successfully.

      1. To view the results go back to your Library Manager and highlight your inverter cell. There should be a new view called av_extracted. If you open this file (use shit-f to display the fet's) it should look simular to your schmatic except now it has several capacitors and a substrate diode. You can now simulate this schematic like you did before.