Cadence Design Tools

Cadence Tools  |  ECEN 5837 (Mixed-Signal IC Design)

AMS C35 Inverter Example

Part IV: Verilog-A and Hierarchical Editor

This tutorial builds on Part I to introduce use of analog hardware description language (AHDL or Verilog-A) in your designs and simulations. Verilog-A allows functional descriptions of analog blocks, which can be very useful for fast simulations of simplified blocks, emulation of driving circuitry and loads, and for test-bench simulations. Here, we add a functional analog Verilog-A view to the inverter example. Of course, a more typical functional view of an inverter is as a digital Verilog block, which will be introduced in Part V. The Hierarchical Editor is also introduced in this tutorial, which is used to specify which views in the hierarchy to use for simulation (e.g. functional or circuit based).

1.       After completing Part I, close any simulation or schematic windows.

2.       In the Library Manager, create a new Verilog-A view of your  inv1  cell (File --> new --> Cell View, or select the inv1 cell and type  veriloga  into the view column)


 


a.       Select the VerilogA – Editor  Tool, which names the view  veriloga  by default (but you can change the view name as you wish).

b.       The  Invoke Modelwriter  window pops up.

c.       Select Cancel to use a text editor to enter your own code.

                                                   i.      In the future, you can select OK to open the Cadence Modelwriter to automatically create code from a list of parameterized default cells (covers a few common functions). You are welcome to try a few cells with the Modelwriter, which can be useful as you get used to Verilog-A coding. You can also add a sample Verilog-A library and view the code for many examples by adding the following to your Library Path:

                                                 ii.      Library: ahdlLib   Path: /usr/local/cadence/IC446/tools/dfII/samples/artist/ahdlLib

                                                iii.      You should also reference the Affirma Verilog-A Language Reference manual on the website.


 


d.       The text editor pop up has the default template information entered, including the cell name and input and output ports, as defined in your current symbol view. If you are creating an entirely new cell, then the I/O would be empty. You would enter the complete description manually, then when you save and exit a new window would ask you if you want to create a symbol --> then auto symbol generation works the same as from the schematic editor.

e.       Enter the following description for the inverter (or copy from the ams_5007_ref course library):


 


f.         Save and exit from the text editor. You should now have a  veriloga  view of the inv1 cell in addition to your other views. Now, we will return to the inv1_sim cell to perform simulation with the new veriloga view and the old schematic view. However, the Hierarchy-Editor is needed to designate which view to use in simulation.

3.       In the Library Manager, create a new view of your  inv1_sim  cell (File --> new --> Cell View, or select the inv1_sim cell and type  config  into the view column)

a.       Select the Hierarchy – Editor Tool, which names the view  config  by default (but you can change the view name as you wish).


 


b.       A blank New Configuration window should pop-up (or it may have default settings, depending on your directory files)


 


c.       Select  Use Template...  -->  spectre . This will fill the form with defaults. Edit the Library list to match your library and add  veriloga  to the Stop List as shown. The View List shows all views that you can descend into in your design and the Stop List contains the views that are used in the simulator (spectre is the Cadence equivalent of “spice” ). You can change your default templates in: ~/hierEditor/templates.


 


d.       In the Hierarchical Editor, you can now enter the views to use for simulation. Following each change, you need to click on the  update  icon. To automatically update after each change, go to:

                                                   i.      View --> Options --> General tab --> select Automatic update.

                                                 ii.      To save this as your default, select File --> Save Defaults --> OK (to save to your project directory).

e.       Change the inverter “View to Use” to  veriloga as shown below:


 


f.         Save this configuration, then exit.  To simulate, re-open the config view by selecting in the Library Manager, with the options below in the pop-up menu:


 


g.       Note that the schematic now says “config” at the top.

h.       From schematic, select: Tools --> Hierarchy Manager (this brings up a new menu item in your schematic).

i.         From schematic, select: Hierarchy-Editor --> Show view found –> apply. This should highlight blocks to show which views will be simulated as below:


 


j.         Note: you can also edit the configuration from the “config” schematic by selecting: Hierarchy-Editor --> Set Instance Binding --> then select any cell instance and use the menu to change the view to use. Then update in the Hierarchy Editor window as well.

k.       Note: If you edit the properties of the  inv1 cell (hotkey q), then you can see the parameters defined in Verilog-A available if the CDF Parameter of view is set to  veriloga.

4.       Run simulation as usual.

a.       Tools --> Analog Environment --> then setup your simulation. Note that the view is  config  instead of schematic.

b.       Setup and run simulations as usual.

c.       Go back and change the view of  inv1  to  schematic  and re-simulate. Note: this tool allows you to easily switch between functional and detailed schematic simulations of individual blocks in your design.

  1. You can also use the Hierarchy Editor to simulate the extracted view of the cell (from the Assura RCX extraction).
    1. In the Hierarchy Editor, add the 'av_extracted' view to the 'View List'
    2. In the 'config' schematic, Set Instance Binding to 'av_extracted' view
    3. Simulate as before
    4. To compare the VerilogA, schematic, and av_extracted results, place multiple instances inf the inverter in the simulatino schematic and assign a different view to each, or run three seperate simulations with a new view each time. In the simulator, select plotting mode 'append' so the simulation results are combined rather than replaced.