Getting Started with First Encounter Place & Route

Use the following brief steps to perform place & route of (simple) synthesized Verilog code in the AMS 0.35u Hit-KIT.

In this tutorial you will fist set up your directory, then generate the files that will build your design for you. Next you will move your synthesized verilog into the proper folder. You will then learn how to run the first encounter. The example that this tutorial goes through also shows you how to sole a few common problems. The first problem is changing the script so that the P&R tool can route the design with out any errors. The second problem is correcting a short that the RTL compiler created.

First Encounter: Bin to Therm example

Setting up the Directory:

1. Create a new directory called " first_enc" inside your current working directory (the directory you type "ams_cds ...." out of)
2. For each new design you P&R you must create a new directory inside of your "first_enc" directory
3. So for this example my directory structure looks like this: proj_5837/first_enc/bin_to_therm

Preparing the files:

In this section we will generate the files and prepare them to work with a specific synthesized verilog file
To edit the file used in this section I transferred the file to my windows desktop using 'SSH file transfer client' and edited it with a text editor. You can edit the file any way you see fit

1. In side of your ./first_enc/bin_to_therm directory we will run a command that will generate all the files that will be needed to P&R your design (except the synthesized verilog of course). For this section you need to know the name of your synthesized verilog file and the name for your top module. In the following procedure every time you see bin_to_them_synth.v replace it with your synthesized verilog file name. Also every time you see bin_to_therm replace it with your verilog top cell name.
2. From the command line (in your ./first_enc/bin_to_therm directory) run the command ams_encounter This explains what all of the switches are for this command; We are using c35b4 technology, the verilog net list is you synthesized verilog file, don't worry about the switches -3b, -v5, or -tlf we won't use these.
3. So to generate all of our files run the command
   ams_encounter -tech c35b4 -vn bin_to_them_synth.v -vt bin_to_therm (but remember to replace bin_to_them_synth.v with your synthesized verilog file name and change bin _to_them to your top cell name). It is IMPORTANT that your specify these file names correctly or else the P&R will fail, it will give you an error stating that it can't find or open the files.
4. This command generates 10 files/folders in your directory. The first thing you should do is place your synthesized verilog code in the "VERILOG/" folder.
5. Next we need to edit the gemma.tcl script. Open the script with some sort of text editor. You will notice that the first part of the file is uncommented and the is commented ('#' is used to comment out lines). The first part sets up all the libraries and loads your file.
6. We will now edit the file so that the script will also place and route your entire design. But as you will find out later you need to be careful and make sure that it dose everything as your expect it to.
7. Edit your gemma.tcl script so that the lines that are uncommented bellow are also uncommented in your file. Read through this file to understand what it is doing and the step it takes to generate the design.



8. Now that every thing is updated in your gemma.tcl script get ready to source your script, if you edited your script in windows make sure you upload the edited script to your directory.

Starting Encounter and Sourcing Script:

1. Start first encounter o ut of your bin_to_therm directory. To do this type encounter at the prompt. A window should pop up this window will show your final design when the program is done.
2. The prompt (which now says encounter 1> instead of magellan/.....) type source gemma.tcl a whole bunch of text will start scrolling down the screen and after a few seconds or minutes a window like the one shown below shows up:



3. If you going to the viewing window you should see a picture like the one before. Play around with the 'view' buttons, they are boxed in red in the in the picture. If you click the 'floorplan view' you will notice a few x's on your design. This means there are errors in your design. You could have also found this out by scrolling up a bit in your command window, it tell you that there are 9 violations.



4. The reason for this error is that there is not enough space for the router to place all the traces. So we need to fix this by increasing the size of the chip area. To increase the chip area or chip utilization we will edit our gemma.tcl script file.
5. To fix this error we need to decrease the utilization, this means that less chip area is for core cells and more area is for filler cells. So we are effectively make the chip larger but keeping the same amount of cells in it. This allows more room for routing.
6. To decrease the utilization we need to change the a line in the gemma.tcl script. The default value has the utilization set to 85% which is usually ok but sometimes you will get an error. The command that set the utilization is "floorPlan -r 1.00 0.85 80 80 80 80" the term .85 is setting the utilization to 85% change this term to .70 this make the utilization 70% which will give the router more room to work with. (edit this script like before and make sure to re upload it) the new command should look like this "floorPlan -r 1.00 0.70 80 80 80 80".
7. Now you are ready to run your newly edited script. Type exit to exit from encounter and clear your current design. go back to 'Starting Encounter & Sourcing Script' step 1 to start encounter and source your script.
8. Make sure that there are no violations this time around.
9. You are now ready to import your design back into cadence. To learn how to do this see the Importing the design from the Place & Route Tool tutorial.
10. After importing your design and running a LVS you will discover that there are a few LVS errors. See the Fixing Shorts & Delimiters tutorial to learn how to fix these errors.