Fixing Shorts & Delimiters

So as you may of noticed, when you LVS the bin_to_therm there is an LVS short error. This is caused by the synthesizer optimizing the block. What happens, as you may of done when you hand made bin_to_therm, is that bin[2] = therm[3] so LVS thinks this is a unwanted short. The section "Fixing Shorts and Hand Editing Verilog" will show you how to solve this issue. It also shows you how to hand edit your synthesized verilog.

Another problem you may of noticed is that LVS will complain about pin mismatch. The reason for this is when you import the synthesized verilog the importer makes the bus delimiters '<' and the place & route tool uses '[' as the bus delimiter. The section "Changing Bus Delimiters" addresses this issue.

Changing Bus Delimiters

This section will show you how to tell Assure not to care about which bus delimiter is used

1. In Assure click the button View Additional Functions then click Use changeLabel Function then click the Modify changeLable Function... button that appears.



2. In the window that appears (shown bellow) under "Replace SubStrings" add ']' to the Old and '<' to New click Add.



3. Again under "Replace SubStrings" add ']' to the Old and '>' to New click Add. After the 2 are entered click Add Command to List (bellow). The window should look like the one bellow.



4. Click OK and run LVS like normal, the nets should now match.
5. So what this dose is when assure reads in all the pin names it substitutes a '>' for every ']' it sees. So to assure they look like the same nets. With this tool can can also change whole net names, for more information see the Assure command ref document and look for the command 'changeLabel()'.

Fixing Shorts and Hand Editing Verilog

This Tutorial will show you how to hand edit your synthesized verilog so that you can remove shorts, technically you could use the changeLabel() function is Assure to make the "same" net but this will also show you how to add components to your verilog. For this tutorial the bin_to_them code will be used.

1. Open up your synthesized verilog for editing. Here is what my code looks like (picture bellow). Every component that is used is described here. Each instance is a CORELIB gate. For example the line where the cursor is a NOR gate that nets 'n_5' and 'n_4' are connected to its inputs and 'therm[6]' is connected to its output.



2. You can see on the line above the buffer that bin[2] is assigned to therm[3], this is short that LVS is detecting. So what we are going to do is add a non _inverting biffer between the 2 nets so LVS won't complain about the short any more.
3. Choose what buffer you want to use out of the 'C35 digital corelib' document in the AMS documents section.
4. I choose to use "BUF2" a simple low power, slower non inverting buffer. It has input A and output Q. To add this buffer i will specify the gate "BUF2" then the instance "I2" then specify what nets are associated with the input and output. Then i will delete the assign statement. The code after i make these changes is shown bellow.



5. Now replace the unedited code with this code in you VERILOG/ folder, in the Place & Route directory. Rerun the P&R tool. Import the stream and verify that there is no longer a short, you may need to use the changeLabel() function (described above) to get a clean LVS.