Mixed-Signal IC Design ECEN 5837 -- Spring 2006 Prof. Regan A. Zane Class: Tues & Thurs, 9:30am - 10:45am, ECEE 1B28 Office Hours: Mon, 3:30pm - 4:30pm | Wed, 10:30am - 12:00pm | Thurs, 12:30pm - 2:00pm, ECEE 1B63

Course Objectives

• Learn to design core mixed-signal IC blocks: comparators and data converters
• Gain experience with system level design flow: top-down and bottom-up design methodologies
• Gain mixed-signal design experience in Cadence CAD tools: mixed analog / digital (Verilog) simulation, digital synthesis and Place & Route, and final layout, DRC, and LVS

Meeting times

• Tuesdays & Thursdays 9:30am - 10:45am, ECEE 1B28

Textbooks

• Highly recommended: P. Allen, D. Holberg, CMOS Analog Circuit Design, Second Edition
  OXFORD (2002), ISBN 0-19-511644-5
• Recommended: S. Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition
  Sun Microsystems Press / Prentice Hall (2003), ISBN 0-13-044911-3
• See Software page for Cadence tutorials and manuals

Instructor

Prof. Regan Zane
ECEE 1B63 (Down hall from main ECE Office)
Office telephone: (303) 735-1560; Fax: (303) 492-2758
Office hours: Mondays, 3:30pm - 4:30pm | Wednesdays, 10:30am - 12:00pm | Thursdays, 12:30pm - 2:00pm

Prerequisites

• ECEN 4827 or 5827: Analog IC Design or equivalent (see instructor)
• Familiarity with digital design in Verilog -- make up if necessary by reading suggested Verilog text, Part I. Additional useful ref: Coding Styles That Kill!
• Familiarity with UNIX operating systems (using Sun SOLARIS OS in SIMLAB) -- search getting started tutorials on google if necessary.

Grading and required work

• 8 homework assignments worth 5% each: 40% total
• Class participation: 5%
• Final project (55% total):
  • Project milestone #1: 5%
  • Project milestone #2: 5%
  • Project milestone #3: 10%
  • Project milestone #4: 5%
  • Final report: 30%

Course Policies

Deadlines:

• Late assignments and milestones: less than one week late will be docked 50%. No assignments will be accepted more than one week late. All assignments are due at the BEGINNING of lecture on the published due date.

Integrity:

• Zero tolerance for cheating: at any level will result in automatic F for all parties involved
• Homework: Students may discuss homework problems and give hints on design and simulation challenges. However, each student must complete and turn in their own unique designs. Absolutely no copying of design or layout files on magellan accounts is allowed. All students must maintain unique design files in their home directory on magellan throughout the course (available for review by instructor upon request).
• Final Project: Final projects are individual (not team based) unless specifically approved by the instructor.
• All students are bound by the student honor code, visit: Student Honor Code.