Mixed-Signal IC Design ECEN 5837 -- Spring 2006 Prof. Regan A. Zane Class: Tues & Thurs, 9:30am - 10:45am, ECEE 1B28 Office Hours: Mon, 3:30pm - 4:30pm | Wed, 10:30am - 12:00pm | Thurs, 12:30pm - 2:00pm, ECEE 1B63

Overview

• The objective is to design a complete mixed-signal IC from system specification to a final design layout as required for submission to an IC foundry for fabrication
• Topic: project must be specified for a specific application requiring analog I/O (sensing & outputs) with on-chip analog and digital components (data converters, amplifiers, digital logic). One example is a controller for a specific plant (e.g. power converter) requiring sensing of various signals, feedback compensation, and output drive.
• Scope: you are to design the complete IC, including full layout with PADS, and provide simulation results demonstrating operation in the application. Circuit behavior of the system outside of the IC can be implemented using functional (verilog, verilog-A) and / or circuit blocks.
• Core blocks: your project IC must include analog and digital blocks. You are welcome to reuse blocks developed in the homework assignments.
• Final design includes matching top level schematic and layout views with pads that are design rule check (DRC) and layout-vs-schematic (LVS) clean
• All students are to perform individual final projects (no groups) unless specifically approved by the instructor
• The project is graded based on four project milestones and the final report. The standard grading policy applies to late project milestones.

Project Milestone #1: Proposal

• Topics should be selected and discussed with the instructor at least one week prior to the proposal due date
• The complete written proposal must include:.
  • Description of the overall application, including an overall system block diagram
  • Purpose or benefits of implementing mixed-signal IC in application
  • Functional blocks / required operation
  • Input and output PAD definitions: names, specs on voltage and current, speed, etc.
  • Block implementation: briefly describe how each IC functional block will be realized (e.g. "diff in, single out folded cascode amp", "verilog code state-machine", etc.)
  • Timeline: detailed design timeline for each block and top level integration, clearly designating results to be included in each milestone
  • Proposed simulation results: what simulations will be used to verify complete IC operation?

Project Milestone #2: Functional and packaging report

• Report to include all of the following:
• Simulations of functional IC operation
• Complete I/O description and layout area estimation for IC
• (not requried for Spring 2006) PAD cell selection for all I/O
• (not requried for Spring 2006) Layout of padframe based on estimated area and PAD cells
• (not requried for Spring 2006) Package selection and bonding diagram based on initial padframe

Project Milestone #3: Intermediate design review

• All students are required to prepare a Power Point presentation for the in-class design review
• 10 minutes maximum, well organized and easy to follow
• Overview project plan and results from milestones 1 and 2
• Present new results demonstrating complete circuit design and simulations for individual IC blocks

Project Milestone #4: Full IC simulations

• Report to include all of the following:
• Complete circuit level simulations of the top level IC
• Full design, layout and verification of individual IC blocks
• PAD cell selection for all I/O

Final project report

• The final project report must include the following sections:
• General Overview: marketing level highlight of IC, key features
• System Description: block diagrams & (brief) description of using your IC in a complete system, table of pin-out, pin descriptions, allowable pin operating voltage or current ranges
• General IC Operation: block diagrams & description of internal IC operation
• Implementation Details: description & operation on each sub-block
• Verification: full DRC and LVS results, simulation results for sub-blocks and top level IC
• Conclusions
• Schematics: attach schematics of the complete design and sub-blocks and verilog code
• Package: details on selected package and bonding diagram
• Testing Plan: describe a testing plan that could be performed at the IC packaging house for functional verification of the IC, including required equipment, testing configuration, procedures, and specifications. Testing Plan Example.