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The purpose of ECEN5503 is to introduce you to the basic concepts of computer system design and architecture. This course will not assume any knowledge of computers or digital logic, however you are expected to have a working knowledge of at least one programming language.
We shall begin with a discussion of digital logic design, including combinational and sequential logic (Appendix A). Following this, assembly language and machine language will be described (Chapters 1 and 2). We will introduce a model machine, SRC, and formal language for machine description, RTN (Chapter 2). We will then cover two real machines, the CISC Motorola MC68000, and the RISC SPARC (Chapter 3). The heart of the course will be the coverage of computer design at the gate level, including the control unit (Chapter 4). We will discuss pipelining, superscalar machines, and several other aspects of modern computer architecture (Chapter 5). We will also cover computer arithmetic (Chapter 6), input/output (Chapter 7), and memory (Chapter 8). We will also cover peripheral devices (Chapter 9), and will conclude with a discussion of computer communications and networking, and the Internet (Chapter 10).
Evaluation will be on the basis of:
a set of homework problems (25%),
one midterm examinations (25%),
a project (20%)
and a final examination (30%).
Unless otherwise specified, homework problems will be assigned on Wednesday and will be due the following Wednesday.
Late homework will not be accepted.
Grades will be assigned according to the uniform grading system:
A - superior/excellent
B - good/better than average
C - competent/average
D - minimum passing
F - failing
Preliminary Assignment: Read Chapter 1 in the text.
| No. |
Topics |
Lectures |
Chapter |
| 1. |
Views of The General Purpose Machine |
2 |
Chapter 1 |
| 2. |
Combinational Logic, Truth Tables |
1 |
Appendix A |
| 3. |
Boolean Algebra, Combinational Logic |
2 |
Appendix A |
| 4. |
Digital Components, Speed, Performance |
1 |
Appendix A |
| 5 |
Sequential Logic, State Machines, Registers |
2 |
Appendix A |
| 6. |
Machines and Machine Languages |
2 |
Chapter 2 |
| 7. |
Informal and Formal Descriptions of SRC |
1 |
Chapter 2 |
| 8. |
Implementing Register Transfers at the Gate Level |
1 |
Chapter 2 |
| 9. |
The MC68000 |
2 |
Chapter 3 |
| 10. |
RISC vs. CISC |
1 |
Chapter 3 |
| 11. |
The RISC SPARC |
1 |
Chapter 3 |
| 12. |
1-Bus Processor Design |
2 |
Chapter 4 |
| 13. |
2- and 3- bus Processor Designs 2 Chapter 4 |
|
|
| 14. |
Reset, Exceptions |
1 |
Chapter 4 |
| Midterm EXAM |
Appendix A, Chapters 1-5 |
|
|
| 15. |
Advanced Processor Design: Pipelining |
3 |
Chapter 5 |
| 16. |
Other Advanced Topics; Microprogramming |
2 |
Chapter 5 |
| 17. |
Computer Arithmetic |
4 |
Chapter 6 |
| 18. |
Memory |
4 |
Chapter 7 |
| 19. |
Input/Output |
3 |
Chapter 8 |
| 20. |
Peripherals |
3 |
Chapter 9 |
| 21. |
Serial Communications and Local Area Networks |
2 |
Chapter 10 |
| 22. |
The Internet |
2 |
Chapter 10 |
|
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