Main+ISR - this is essentially the same software architecture as a Cyclic Executive, however, Main+ISR may be much simpler in that it normally has just one main loop and a small number of ISRs compared to a Cyclic Executive which may have multiple loops operating at different frequencies.
MBE - Multi-bit Error, a condition when more than one bit in a word is in error - typically this can not be corrected.
Memory Hierarchy - the whole memory system design from the fastest and typically smallest devices to the slowest and typically largest devices - e.g. L1/L2 cache, main memory, and flash.
Memory Mapped I/O - I/O devices which can be read or written can be mapped into the address space of a processor allowing software to simply update an address in order to write to the device or read an address to read from the device - the device must respond to the addressing by the CPU, I.e. decode it and then read/write data on a bus which both the device and CPU interface with.