University of Colorado
Department of Electrical and Computer Engineering
ECEN 4633/5633 Hybrid Embedded Systems
Class T: 5:30-8:00 ECEE-1B28
Laboratory T: 5:30-8:00 ECEE-1B79
Instructor: Dr. Kimberly E. Newman
Office: ECEE-120 Phone: 735-2287
E-Mail: Kimberly.Newman@colorado.edu
Office Hours: M R 10-12:00, and by appointment
Teaching Assistant:
Pre/Co-requisites: Knowledge of microprocessors/microcontroller based systems and assembly language programming (e.g. ECEN 4613/5613 Embedded System Design), High-level programming (e.g. C, C++, Java)
Course Texts:
Zainalabedin Navabi, “Embedded Core Design with FPGAs”, copyright 2007 McGraw-Hill, ISBN 978-0-07-148470-1 [REQUIRED]
There are 4 free on-line reference handbooks:
• Nios II Processor Reference Handbook (Nios PRH)
• Nios II Software Developer’s Handbook (Nios SDH)
• Embedded Peripherals (EP)
• Embedded Design Handbook (EDH)
All are available at: http://www.altera.com/literature/lit-nio2.jsp
The material is available on a per-chapter basis, allowing students to download and print specific concepts. The handbook acronyms (Nios PRH, Nios SDH, EP, and EDH) will be used to assign reading.
Course Description
The scope of embedded system design platform has expanded from the traditional system of a programmed microprocessor or microcontroller to the use of “embedded cores and processors”, and reconfigurable devices as components of a digital system. This growth in technology provides greater design flexibility, in that the system architect/designer can choose the mix of hardware and software components of a system, and have more control over the computing architecture and organization of the system.
Hybrid embedded systems course will address embedded systems design using embedded cores and processors. Students will learn how to design, develop, and use a soft-core processor implemented on an FPGA. In due course, students will learn hardware design, software design and SOPC design techniques.
Hardware Design
• Understanding the architecture of a typical development board and functionality of on-board devices
• Understanding of the Altera chip architecture and the functional of its components
• Understanding of the Altera internal microprocessor Bus Architecture
• Defining a system architecture using the Altera FPGA chip and the on-board modules
• Designing and implementing a custom hardware and its interface with the bus architecture
Software Design and Using State-of-the-Art Design Environments
• Understanding the details of system software components (boot loading, initialization, system stack, system calls) and interfacing hardware with high-level and low-level techniques
• Understanding the capabilities of Quartus II Design Environment for design and verification.
SoC designs result from the increased density of functionality that can be placed on a single chip. SoC designs are characterized by functional complexity which can not be effectively accommodated by traditional hardware-only design methods. The embedded computer system architectures on these chips include concurrent software executing on one or more processors, operating system schedulers, and hardware models, including application specific functionality, buses and networks. Through lectures, readings, presentations, discussions, and projects, this course presents the fundamental models and design steps that enable the design of SoC from the software through the logic levels, with the goal of integrating multiple components and other systems.
At the end of this course, students will be able to:
• Understand the methodology to specify, design and implement a microprocessor based SoC.
• Employ computer aided design tools to design and implement a microprocessor based SoC.
• Understand the concepts behind hardware/software co-design and the advantages in using hardware/software co-verification tools.
• Calculate the specifications and bandwidth requirements of a given embedded system.
Assignments and Examinations:
Examinations are intended to measure your individual mastery of the material. Exams concentrate on your understanding of the important concepts, rather than your ability to memorize details. All major examinations will be held in class with exact dates determined in class. The exams will generally test your knowledge of assignment material, so you are responsible for mastering all lab, homework, and programming material submitted with other partners, as if you did all the work by yourself. All exams will be open book and open notes (unless otherwise stated). The nature of the course material is such that the final exam must be cumulative.
Lab Exercises: Laboratory exercises are meant to develop design and implementation skills in both hardware and software. These exercises will be due every 1-2 weeks.
Grading
Assessment Design/Grades:
(15 %) Exam I
(15 %) Exam II
(20 %) Homework Assignments
(25 %) Lab Exercises
(25 %) Project Presentation - During FINAL exam period
Grades are as follows:
A – “Superior/Excellent”, 90 – 100%
B – “Good/Better than Average”, 80 – 89%
C – “Competent/Average”, 70 – 79%
D – “Minimum Passing”, 60 – 69%
F – “Failing”
Examinations: Exam material will follow material covered in the lectures and homework exercises. The final exam for this course will be a series of student project presentations. ALL STUDENTS ARE REQUIRED TO ATTEND THE PRESENTATIONS.
Laboratory: There are approximately 8 laboratory assignments. Laboratory assignments will be posted on Blackboard. In most cases, there will be separate assignments for undergraduate and graduate students. Students can either work individually or in pairs. Upon completion of the laboratory assignment, the student/group-pair will give a demonstration to the T.A. or the instructor and submit an electronic copy of the documented source code via the digital drop box on blackboard.
Project: Semester project is a project of choice. Students can work individually or in groups of any size. Note that the size/complexity of the project is directly proportional to the size of the group. For example, the size/complexity of the project for a two-person team will be twice the size/complexity of a single-person project.
Prior to starting the project, the student or group will submit a short abstract of the project which entails
At the end of the semester, a report and demonstration of the project will be presented during the final exam period.
Tentative Course Outline
|
Week |
Text |
Topic |
|
1 |
Ch. 1 Nios SDH |
General Introduction. Goals for the course. Hybrid embedded systems. Laboratory #1 – Basic I/O & tool flow. |
|
2 |
Ch. 5 Nios SDH |
FPGA architecture and layout. NIOS II architecture and configuration options. Laboratory #2 – Peripherals and External Memory Interfacing. |
|
3 |
Ch. 6 Nios SDH |
Monitors, in-circuit emulators, debuggers, monitors, software engineering, debugging using software. Laboratory #3 – Debugging and System Monitoring |
|
4 |
Nios PRH |
Memory Hierarchy Catch up on labs & review session |
|
5 |
Nios PRH |
Exam I Cache Schemes |
|
6 |
Nios EP |
Timing, design timing-constraints and requirements Laboratory #4 – Interrupts/Polling and System Performance |
|
7 |
Ch. 7 Nios EP |
Custom Interfaces Laboratory #5 – External Sensor Interfacing |
|
8 |
Ch. 9 Nios EDH
|
Laboratory #6 – Multicore Systems |
|
9 |
Nios EDH |
Design optimization trade-off analysis. Catch up on labs & review session |
|
10 |
TBD |
Exam II Hardcore vs. Softcore |
|
11 |
TBD |
RTOS Design for SOPC Laboratory #7 - Embedded Design with RTOS |
|
12 |
|
Finish labs and turn in proposals for projects. |
|
13 |
|
Work on projects |
|
14 |
|
Work on projects |
|
15 |
|
Work on projects |
TBD – to be determined