Adding I/O Pads to the Design
This tutorial starts with a discussion about the different I/O pads available and the where to find information about them.
All the I/O pads are found in the IOLIBV5_4M, IOLIB_4M and the IOLIB_ANA_4M libraries. The first one is a 5V library the second one is the standard digital library and the last one is the analog pad library, respectively. The analog library also includes the pad stacks as well. The main difference between the digital and analog libraries is that the digital pads have input and output buffers on them, whereas the analog pad can be any thing from just the pad to having an input resistance and protection diodes.
There are many different pads in each of the libraries. You should check out the following information to choose yours appropriately.
For more information on the IOLIBV5_4M go to launch Magellan/usr/local/AMS_3.70_CDS/www/databooks/c35/databook_io_v5/index.html
For more information on the IOLIB_4M click here.
For more information on the IOLIB_ANA_4M click here.
For the standard process, tech_c35_b4, you should use the *_4M libraries.
The following tutorial will take 3 inverters from the CORELIB and create a die to be packaged in a 150 mil SOIC 8 pin package.
- Before you get started you should take a look at the packaging options liked here. At the beginning of the pdf all the different package types are defined. The number of pins and the cavity size are going to be your main concerns.
- The cavity size dimensions are in mil's unless otherwise noted. You do not want your cavity size much larger then your final die area because the in most cases angle between the bonding wire and the die edge must be larger then 45 degrees.
- For this tutorial we will choose the SOIC package with a cavity of 90x130 mils. This is approximately 2.286 x 3.302 mm.
- Next we need to choose our pads. A power and ground pad are needed. 3 inout and 3 outputs are also needed.
- When looking at the pad options we notice that we only have a few options with the input buffer but quite a few with the output buffers. So for the input buffer we will choose the one with no pull up or pull down, the ICP. For the power and ground pins we will choose the ones that supply power/ground to every thing, VDD3ALLP/GND3ALLP respectively. For the output buffers we choose the strongest and most power hungry ones. These are the BU24P, they are a 24mA drive strength and have a very little delay.
- Now that every thing is chosen we will go to cadence to design the schematic and lay it out. These cells are just like using the CORELIB cells; there is a schematic and layout version. But in layout we will also add a few extra spacers cells and corner cells that just connect every thing together
- In schematic we will just add 3 INV0 inverters from the CORELIB library. Next we will add 3 BU24P output pads and 3 ICP input pads and 1 power and ground pad (VDD3ALLP/GND3ALLP). All the pad cells are from the IOLIB_4M library.
- You should connect your power and ground pads to the appropriate voltage, connect the I/O pads to the correct inputs and outputs. Next add labels to each one of your pads. Your schematic should look like the following.
- Now we will go to Layout this design. The first thing to do is to build the pad ring correctly. To make things a bit cleaner i will open a new file called inv_pads and then add this to my final layout.
- The first thing to do is add all the pads and make sure they are in the correct order. The lay out should look like the following pictures.
- Each one of the pads is 100u so they will all line up perfectly. Start in the any corner you chose, you must line up each of the pads perfectly. The best way i have found is to zoom in on the corner between the two pads. You must move the pads so they perfectly touch like what is shown in the figure bellow. The zoomed in picture is of where the white arrow is pointing
- Now we will make all the pads touch, on the one side, like in the previous step. The final result should look like the following picture
- Now you will add the corners and spacers to the layout. From the IOLIB_4M add the CORNERP cell. Rotate it and place it in the top left corner above all the cells you just put together. (If you haven't noticed we are going to build this ring by starting in one point and working back to that point). To line up the corner use the metal 2 ring on the outside, like you did before. The results are shown below.
- Now we will add the spacer for the top part of the chip. Use PERI_SPAVER_100_P from the IOLIB_4M any of the other spacer could be used, but this one will give use plenty of room to add the internal cells. Attach it the same way as before.
- Repeating the previous steps add the reset of the cells, adding corners and spacers were necessary. The result should look like the following picture. Note One check that you can do is after the last piece is placed check to make sure the other side of the last piece is in the correct location.
- Now you should run a DRC and LVS. To run the LVS add labels to the pads, note the pads are built with every metal layer, but i chose to use the pd pin (the pad pin). Make sure to add vdd and gnd labels to the 'A' pin NOT THE PAD use metal 2 pins. Also you will need a schematic, copy the schematic from your other file and just delete the inverters.
- Bellow is a list of the DRC errors that are generated (with no_coverage and no_generated_layers switches set), if you investigate you will find that all these errors are in the standard cells, no idea why they have so many DRC errors in their standard cells. Basically any thing that is part of the pad core cell is an ok DRC. It is recommended that you DRC your entire design before you place it in the pad to make sure that you are only getting the pad DRC errors.
- The follow pictures show the LVS errors that are generated and the schematic that was used. These errors are because in their standard cells the connect all the different vdd's to the pin A. So again you can ignore these LVS errors.
- Next add the 3 inverters and do a full DRC and LVS. The following pictures shows the final layout and the DRC errors. You will notice that the floating gate errors are gone but every thing from before is still there.
- Next is the LVS errors one can see that there is only the same ones as before.
- The wire bonding part will be brought to you later.