Cadence Design Tools
AMS C35 Inverter Example
Part V: Mixed-Signal Simulation
This tutorial builds on Part IV to introduce use of the mixed analog and digital simulator in Cadence (spectre-Verilog). This powerful tool allows co-simulation of ideal Verilog (or VHDL) code together with Verilog-A and spice level circuits. The interface between digital and analog blocks (effective A/D and D/A) can be defined using simplified built-in models.
1. Create a mixed-signal schematic with your inv1 cell and an inverter from the AMS CORELIB library, INV0
a. Create a new cell with schematic view (or copy your inv1_sim cell): inv1_sim2
b. Add the same components as in your inv1_sim cell, plus the INV0 cell (symbol view) from the AMS CORELIB library as shown:
c. Save & close the schematic view
2. Create a config view using the Hierarchy-Editor
a. Use the view and stop lists shown below.
b. Use the symbol view for INV0 and the schematic view for your inv1 (you can later come back and try the veriloga view for inv1 as well).
c. Save & close the Hierarchy-Editor.
3. Setup mixed-signal options and open the simulator
a. Open the schematic version of the config view of inv1_sim2 from the Library manager (click yes and yes to open both the editor & schematic views)
b. Select: Tools --> Mixed-Signal Opts. (adds Hierarchy-Editor and Mixed-Signal headers to your tool-bar)
c. Select: Mixed-Signal --> Partitioning Options
i. Change analog & digital stop views to match the stop views in your hierarchy editor (as below)
d. To view the analog / digital configuration, select: Mixed-Signal --> Display Partition --> All Active (this will color code signals as analog, digital, or mixed; use Interactive to see the color code)
e. Setup the analog/digital interface for cell inv0
i. Select: Mixed-Signal --> Interface Elements --> Instance; this tool is used to configure how the digital block reads analog inputs and how digital outputs are seen by analog cells (effective A/D and D/A). Selecting Instance changes only that instance in your design; you can also select the cell or library or specific terminals. In this case, only instance options can be used since you do not have write access to CORELIB.
ii. Look at the default input and output settings, which are pre-configured for the AMS library with 3.3V supplies. Leave the defaults (come back later and change to see the effects). Note: a2d_tx is the time analog signals can operate between v0 (low) and v1 (high) before an error is given in the simulation (due to invalid input).
4. Run the simulation
a. Select: Tools --> Analog Environment from the config view of the schematic
b. Select: Setup --> Simulator/Directory/Host, then select spectreVerilog simulator (as below). Note: Project Directory is where simulation files are placed. You should periodically erase this directory to avoid filling the partition on magellan (and/or create and use a directory in the /magellan/scratch partition)
c. Setup the simulation as usual (e.g transient, 50us run time) and run the transient. Two windows will pop-up: one for digital simulator messages, one for analog simulator messages.
d. Plot the two outputs (digital and analog). Separate the two plots.
e. As seen, one is analog, the other is digital (with outputs st1 and st0). Note that if the two are put on the same plot (same y axis), that the digital is by default considered 0V to 5V (independent of the Interface Element designation). This is irrelevant and is only an artifact of the plot tool.
f. Go back and add an analog part (such as resistor to ground) to the output of the digital INV0 block, and you will see the output become 0V to 3.3V as defined in the Interface Element. You can also change the stop view for either design. Note: the spectreVerilog simulator will not run unless at least one component is digital.