Cadence Design Tools
Configuring and using the AMS C35 process HIT-Kit (magellan)
The AMS C35 HIT-Kit is a complete design library for the AMS 0.35u process with additional configuration scripts to automate the required links between many of the Cadence tools. The library includes (1) device models for transistors, resistors, capacitors and inductors with links to symbols, model files (w/ typical, corner, and statistical data), and automated “p-cell” layouts; (2) digital and I/O libraries with symbols, schematics, reduced layout (includes geometry & connections, complete layout inserted by foundry), Verilog code, timing info, etc.; (3) layout files (display.drv, DIVA & ASSURA DRC, LVS); (4) libraries and configuration tools for synthesis (buildgates/PKS) and automated place & route (Silicon Ensemble/PKS), among others.
Starting the kit & creating a library:
1. Update your .cshrc on magellan with:
a. prompt> cp /usr/local/cadence/cadence/setup/sample.cshrc ~/.cshrc
b. Source the new .cshrc by typing: >source .cshrc (or log out and back in)
2. Create a project directory for use with the kit
a. Note: never start cadence directly from your home directory. It will create many setup files that may be difficult to detect and override later.
b. Create a directory for this process which you will use for all course projects:
1. prompt> mkdir ~/proj_amsc35
3. You now start cadence using the HIT-Kit (the kit calls the appropriate command for cadence). Move (cd) into the new directory proj_amsc35, then start the kit:
a. The first time in this directory, use:
1. prompt> ams_cds –tech c35b4 –mode fb
b. This configures your directory (proj_amsc35) for the c35b4 process, opens cadence in the “icfb” or front-to-back mode.
c. In the future, you do not have to use the –tech c35b4 flag, since the directory has already been configured. Simply start the kit from that directory with:
1. prompt> ams_cds –mode fb
d. You should see the Cadence CIW window pop up, with many messages about loading the HIT-Kit, followed by a “what’s new” window and the library manager. (ignore the “prtconf:..” error)
e. The Library Manager window will also pop up. This is the primary window for managing your design files and creating new designs. Your window will look similar to (but not exact) the window below (click “Show Categories” for useful sorting) .
4. Create a new library for use in the class (later in the course, you can create additional libraries for new homework assignments or your final project if you choos):
a. Create a new library (e.g. 5007_<your_name>): File --> New --> Library...
b. Select attach to an existing techfile , then select TECH_C35B4
You are now ready to work in the library.
6. When selecting parts from the kit, use the following libraries
a. A_CELLS: Analog cells are only included with symbols and layout frames for our reference. These must be purchased to be included in the kit (we do not have them)
b. BORDERS: Use the border 'A4' for documenting your circuit schematics. Do not use a border for your simulation setup schematics.
c. CORELIB: select your digital logic from here, symbol view for schematics, layout view for layouts. The layouts only include the frame and metal connections for use. The complete layout would be inserted at the foundry (to protect their IP)
1. NOTE: When simulating digital cells as schematic “cmos_sch view”, you must have vdd! and gnd! labeled in your schematic.
d. IOLIB_**: various input-output PAD cells for final layouts
e. PACKAGES: package models (wire inductances, resistances, etc)
f. PRIMLIB: Use this library for all of your devices: nmos4, pmos4, various resistors & caps. They will link to their model files with parasitics included. Also provides links to corner and monte-carlo statistical models. You can also insert these cells into your layouts for automatic layout generation of devices “p-cells”.