TA: Dan Walkes, E-mail: Daniel.Walkes@colorado.edu, TA Web-Link
Office Hours: Tues 7:00-8:30 PM and Thurs 3:30-5:00 PM in ECEE 185 Lab.
Classes: Held on Wed. 6:30-9:00 pm, with lectures in ECCR 131
Labs: labs/demos wil be held in ECEE 185
New Project Development Lab: EE 123
Special Thanks to Industry Sponsors:Wind River Systems, RTI (Real-Time Innovations), and TimeSys.
(Need Directions? -- Engineering Center Map)
Non CU students may register through CAETE:Registration Info
Prerequisites: Embedded System Design (recommended) and C programming proficiency (required)
Other courses in Embedded Systems Program: Embedded Systems Project and Embedded System Design. The three courses may be taken in any order, but the recommended order is 1) Embedded System Design, 2) Real-Time Embedded Systems, 3) Embedded Systems Project.
Course Project Detailed Description Page
Selected Sites with Robotics Info (5-DOF Robotic Arm Projects)
Selected Sites for Hardware (x86 Architecture, PCI, Audio, and Computer Vision / Optical Navigation Projects)
Selected Sites for Computer Vision and Image Processing Info and Code
Selected Sites with Chipset Docs and Databooks(VoIP and Video / Peak-Up Projects)
Selected Sites with Standards Info (PCI, VME, POSIX, NTSC)
Linux/RT and Linux Video Page
In this course, students will design and build a microprocessor-based embedded system application requiring integration of sensor/actuator devices, A/D and D/A I/O interfaces, microprocessor, commercial real-time operating system, and multi-tasking application software. The course focus is on the process as well as fundamentals of integrating microprocessor-based embedded system elements for digital command and control of typical embedded hardware systems. Standard project options include: 5 DOF robotic arm, laser serial communications, or digital video processing. Topics include: PCI (PC/104+ and Compact PCI), ISA (PC/104), and VME bus architectures and programming; device firmware; system firmware architectures; microprocessor and I/O architectures; ECC/EDAC memory architectures; interrupt service routines; real-time clocks/timers; real-time kernel configuration and extension; main loop designs; multi-tasking; inter-task communication; cooperative and priority pre-emptive designs; hard real-time scheduling theory and design (Rate and Deadline Monotonic), latency, response time, system performance, and development and testing techniques. Students configure and extend a priority pre-emptive multi-tasking operating system for a student-built hardware/software embedded system. The student will be introduced to the full embedded system lifecycle process in this course including: analysis, design (using extended finite state machine specification tools), programming, hardware assembly, unit testing, integration and system testing.
Each semester guest speakers are invited to provide informational and/or technical presentations on the use/application of embedded systems in industry. Speakers are recruited from the aerospace, robotics, telecommunications, medical systems, systems software/architecture, virtual reality/multimedia/entertainment and embedded tools/systems industries. Please send mail if you have interest in speaking to my class and work in an embedded systems industry! -- Sam.Siewert@Colorado.EDU
Note: Handouts will be distributed occasionally.
All labs are due on Wednesday nights in class or by e-mail submission.
Labs submitted after the due date will be accepted until the following Monday, but will receive only partial credit. Labs later than 5 days will receive no credit.
Working Together and Re-use of Code - You can work with a partner on labs, but must submit original work individually and carefully note who you worked with and specifically what aspects you collaborted on - code for labs should be original and not a duplicate of anyone else's solution! The same goes for projects. Code from outside sources (shareware) can be incorporated into projects, but must be clearly cited and given credit. Proper citation and credit should be given to all outside help and/or materials incorporated into projects or labs. All students are expected to provide proper citations and to follow CU's academic honesty policy in this regard.
In general the grading is weighted such that 1/3 of the grade is based upon mastery of theoretical material, 1/3 based upon performance on hands-on labs, and the final 1/3 based on application of theory and development methods to the final project. Lab Work -- 35% Initial Quiz -- 5% Midterm -- 20% Final Quiz -- 5% Project -- 35% Tentative HW breakdown details 1 Intro assignment @ 5% = 5% 3 labs @ 10% each = 30% The project can be an individual or joint effort to build an embedded system application, including either: a) a standard project (e.g. 5 DOF robot, laser/IRDA/RF communications, digital video, voice/IP, or optical navigation), b) a hardware driver interface or firmwared project with software demo of your own design with instructor consent, c) real-time software application of your own design with instructor consent. The two exams will be straight-forward tests of your understanding of the theory and survey portions of the course.
08/25 Introduction - Lecture 1 - Course goals - Course project - Course grading (see policy below) - Video Tape: Project from Previous Semesters (Robotics, Video, Audio) - Wiley Software Engineering Encyclopedia - Wiley EE Encyclopedia Hands on lab night #1 - Tornado/VxWorks lab introduction (code build, load, and logistics) - Brief VxWorks Demo - Programmer's Guide - Chapter 2, Basic OS - Tornado host development system - WDB target server - "launch" tool target manager - Windshell - Windview - "Software Logic Analyzer" - Browser Assignment #0 -- handed out Read: RTECS (Real-Time Embedded Components and Systems) - Preface and Chapter 1 - Introduction INITIAL QUIZ REVIEW - Terminology Overview 09/01 Fundamentals of Real-Time Theory - QUIZ on Terminology Overview, Lecture 2 - What's makes distributed, real-time, embedded multitasking systems challenging? - Best effort, Hard real-time, Soft real-time - Scheduling Class Taxonomy - Best Effort scheduling (Round-Robin Timeslice Scheme - Review) - Intro to Fixed priority preemptive scheduling - Intro to Dynamic priority scheduling - Utility Curves Paper: Liu and Layland Rate Monotonic paper Read: RTECS - Chapt. 2 - Processing Section through RM Derivation INITIAL QUIZ - On Terminology 09/08 Fundamentals of RT Theory Cont'd - Services and High-Level Design - Lecture 3 Real-Time Services - What a Service Release Timeline Really Looks Like - The CPU, I/O, Memory Resource Space (Characterizing RT Applications) - Intro to Timing diagrams (interference) - Intro to Hard real-time safe resource utilization bounds Case study #1: High-Level RT System Design Examples EXAMPLE - Space Infrared Telescope Facility Instrument Control (launched on August 25, 2003) - The hard real-time requirements and performance - What worked, what didn't and why - Overview Presentation - The Test Image EXAMPLE - DATA-CHASER Shuttle Payload - PowerPoint, DATA-CHASER HTML Paper: Audsley DM paper Assignment #0 -- DUE Assignment #1 -- handed out 09/15 RM/DM Policy and Feasibility Test Derivation - Lecture 4 Rate Monotonic Policy and Feasibility Overview - Rate Monotonic Assumptions and Constraints - More on Fixed priority preemptive scheduling - Overview of Derivation of RM LUB - Hard real-time safe resource utilization bounds - More on Dynamic priority scheduling (Earliest Deadline First and Least Laxity First) - EDF and LLF Overview Introduction to Feasibility Tests - Sufficient Tests - RM LUB, DM - N&S Tests - Scheduling Point - Completion Test Deadline Monotonic Policy and Feasibility Overview - DM Sufficient Feasibility Test - DM Sufficient and More Necessary Test Beyond RM and DM: - Scheduling Point Feasibility Test - Completion Test Feasibility Test - Sufficient vs. Necessary and Sufficient Feasibility Tests - Computational Complexity of Feasibility Tests (O(1), O(n^2), O(n^3)) RMA Analysis Tool Vendors - RapidRMA, TimeSys Read: RTECS (Real-Time Embedded Components and Systems) - Finish Chapter 2 Processing Section Hands on lab night #2 (code build, load, and signle step debug) - VxWorks TCB (Task Control Block) (Read/Browse POSIX section of VxWorks Ref. Man. 5.4) - VxWorks example code demo - Using GDB to debug a task or the system 09/22 RM Implementation Challenges: Real-Time Service Implementations, Synchronization and Shared Resources - Lecture 5 Paper: Priority Inheritance Protocols "Priority inheritance protocols: an approach to real-time synchronization", Sha, L.; Rajkumar, R.; Lehoczky, J.P.; Computers, IEEE Transactions on, Volume: 39 Issue: 9, Sep 1990. Paper Available on:IEEE Publications Page HW and HW+FW Implementations of RT Services - ISRs, task canonical structure, and task/service release - FPGA/ASIC-based State Machines for Offloading - Microprocessor/Microcontroller Offloading - DSP Offloading SW Implementations of RT Services - Main+ISR Executive - Cooperative Non-Preemptive Threads - Callbacks - Continuation Functions - Software State-Machines - Priority Preemptive Run-to-Completion RTOS - Time-sliced Traditional Best Effort OS Synchronization and Resource Issues: - Problems with Blocking (resources other than CPU, e.g. I/O) - Break up into more threads (better scheduling control) - Interrupt driven I/O - e.g. Programmable FIFOs - Model Blocking Time - Priority inversion (general concept) - Unbounded priority inversion problem (mutex C.S.) - Priority inheritence - Priority ceiling Other Practical Problems - Solutions: 1) Estimating C (execution jitter) - use WCET 2) Period jitter - transform to highest frequency 3) ISR and context switch overhead - add to WCET 4) Deadlock/Livelock - HW Watch Dog 5) Bad code spinning and wedging - Sanity Monitoring Case Study #2: Mars Pathfinder (As presented from multiple perspectives) Mike Jones Overview or What Happened to Mars Pathfinder Mars Pathfinder -- WRS Story Mars Pathfinder -- JPL Story Read: RTECS (Real-Time Embedded Components and Systems) - Finish Chapter 2, IO and Memory Sections Assignment #1 -- DUE Assignment #2 -- handed out 09/29 Real-Time Service System Integration and IO (Post Release Service IO and VxWorks Inter-Task Communication) - Lecture 6 Service Synchronization, Communication, and IO - Using Message Queues to Sync Services and for Communication - Using Binary Semaphores to Sync Services - What about IO during Service Execution? Overlapping CPU and IO Cycles - Latency Hiding - Initial Release Input - Block DMA and FIFO Sensor Data - Intermediate IO - Memory-Mapped IO During Service Processing - Hiding IO latency with Overlap System Design with RT Services - Software process: analysis, design, specification, coding, unit testing, integration, system testing, delivery, operations - Implementation characteristics: tasks, message passing, synchronization, ISRs, memory-mapped I/O, bus interface, signals, shared memory, stack/data/heap mgt., comm. interfaces - Specifying the design of real-time software systems Data flow and Control flow (function and interfaces) Extended finite state machines and signal block diagrams MSC (multi-tasking multi-node protocol/comm model) Hands on lab night #3 (code build, load, and logistics) - Processes, threads, and tasks, what's the diff? - VxWorks TCB (Task Control Block) (Read/Browse POSIX section of VxWorks Ref. Man. 5.4) - VxWorks switch hook demo - VxWorks Services Read: RTECS (Real-Time Embedded Components and Systems) - Chapter 3 10/06 Scalable Embedded Systems Architectures Lecture 7 Intro to PCI Architecture and I/O Architectures - Intro to PCI bus architecture and device interfaces - Comparison of PCI with older VME Bus VME Word and block transfer vs. PCI Burst VME Asynch address and data modes vs. PCI Sync A/D 32/64 and Config Space - PCI Plug and Play Concept - Embedded System PCI Form Factors and Standards CompactPCI, PC/104+ (PCI+ISA), PMC, PCI-X 1.0a/b, PCI-X 2.0, PCI-Express Read: Shanley Text, (chapters 1*, 2*, 5, and 6) *=required, others suggested - Discussion on I/O Trends (High speed differential serial) USB PCI-Express 1G and 10G Ethernet RapidIO Other High-speed Serial: Firewire, RapidIO, SAS/SATA - Discussion of ASIC Trends SoC (Yesterday's Board, Today's Chipset, Tomorrow's ASIC) Core + I/O (PowerPC 8xx, 82xx) Reconfigurable (Virtex II) Configurable (Tensilica) IP Modules (CPU Cores, Mem Ctlrs., Local Bus) Off-loading (Today's SW is tomorrow's HW) Hands on lab night #4 (code build, load, and logistics) - The POSIX 1003.1b compliant Embedded system environment (VxWorks) - The POSIX Application Programmer's Interface - POSIX overview: message queues, RT signals, and semaphores - Clocks and timers 10/13 Device Drivers and Characterization of Embedded I/O Lecture 8 I/O interfaces - Digital - Analog (ADC, DAC interfaces) Microprocessor interface types (word or block) - Register-based control, status, data - Higher rate FIFO I/O - Block-oriented 1st/3rd party DMA tx/rx between I/O interfaces and memory - Bus burst transfers and block transfers - system memory map for MMIO devices - DRAM/SDRAM/DDR, BOOTROM, Flash External interface types - CPU local bus IO/MMIO E.g. PCI 2.x, GPIO, DRAM, Flash - Point-to-point or switched devices E.g. RS-232, RS-422, PCI-Express - Network multi-access devices E.g. Ethernet Device interfaces -- introduction to drivers - top half (driver entry point interface to tasks) - bottom half (interface to devices) - ring buffers - blocking/non-blocking - ioctl "swiss army knife" - ISRs and signals/semaphores - scheduled I/O (handle buffering and processing in task) Read: Shanley Text, (chapters 14*, 17*, 18*, 19*, 26, and 28) *=required, others suggested Mid-term Review: Lecture MT-Review Assignment #2 -- DUE Assignment #3 -- handed out 10/20 MIDTERM MIDTERM (1.5 hours) 10/27 Speaker and Mid-Term Solutions GUEST SPEAKER -- Van Culver, CU Real-Time Systems Group, ASL/Gesture Recognition in RT Using a Data Glove and Cameras MIDTERM solution overview/questions - exams returned Assignment #3 -- DUE 11/03 Real-Time Performance, Debugging Issues and Debug Techniques Lecture 11 Architectural and algorithmic causes of execution jitter PowerPC Architecture: PowerPC 8xx architecture review HTML Power PC 8xx and 82xx Architecture Power Point Overviews Xscale Architecture: Xscale Architecture Docs Estimating/Measuring Performance Based on CPU Architecture - Example of how to estimate C for a peak-up algorithm on PowerPC Appendix B, pg. 129 of A Real-Time Execution Performance Agent Interface for Confidence-Based Scheduling - Measuring/Controlling CPU Efficiency - Trace Ports (e.g. IBM PowerPC 4xx series, Strong Arm) - Built-in PMU (Performance Monitoring Units) (e.g. Intel Pentium, Xscale) - External Methods - Logic Analyzer Memory Traces (Cache Misses, DMA, Un-cached access) - GPIO Markers - Profiling Code by Function or Block - Software in Circuit Methods (e.g. CodeTest Trace SW In-Circuit, gprof) - Hardware Supported Profiling (e.g. Intel Vtune, CodeTest HW In-Circuit) - Cycle-based profiling - Event-based profiling - Cache Coherency - Harvard I-Cache, D-cache Architecture - Cache Invalidate, Flush, Lock, Pre-fetch - Measuring/Controlling I/O Efficiency - Bus Analyzers - e.g. PCI Event Traces - Logic Analyzer with Support Package - PCI Bus Performance Tuning - Bus Grant Arbiters and Priority Schemes, Minimum Burst Length - PCI-Express Performance Features - PCI Express Tutorial - Isochronal Virtual Channels - Split Transaction Hands on lab night #5 (boot, kernel, and JTAG debugging) - IEEE 1149.1 JTAG Test Access Port and Boundary Scan Standard - Using a JTAG for BSP Development (VxWorks) - The VxWorks Bootrom Boot Loop and BSP - Kernel configuration, build, and debugging Paper: Zen of BDM 11/10 Embedded Volatile and Non-volatile Memory Devices Lecture 12 Memory Technologies and Hierarchy - Harvard Arch. I-Cache, D-Cache (Separate instruction and data cache) - L1 On-Chip, L2/L3 Off-Chip Cache - SRAM (Fast, but expensive per bit stored) - DRAM, SDRAM, DDR (Double Data Rate DRAM), Quad Rate SRAM ECC (Error Correcting Circuitry) memory - Hardware/Software Design - Hamming encoding for EDAC (Error Detection and Correction) - review handout provided - ECC and maintenance and handling of SBEs and MBEs - Firmware ECC Req'ts: 1) initialize memory fully, 2) handle SBE interrupts, MBE check-stop, and 3) background scrubbing Non-Volatile Memory Devices and Systems - EPROM, EEPROM, NVRAM, and Flash (NAND, NOR, SFDC) - Flash File Systems - TrueFFS 11/17 High Availability vs. High Reliability (Same?)Lecture 13 Definition of High Availability (5 9's) - System is ready to provide service 99.999 % of any given service year - System can crash, but must reboot with minimal interruption to services and returning to fully service availability quickly Definition of High Reliability - Formal methods and testing to prove reliability is designed in and built in - SW Path coverage, statement coverage, and condition coverage criteria - HW Simulation testing with SW drivers - HW built-in test (Built-in Logic Analyzers, JTAG, Built-in Performance Monitoring Counters) - System Safe Modes Recovery Concepts - Conservative Safe Mode Manual Recovery (typical of satellite systems) - Automatic Recovery (typical of high availability sytems) Case Study #3:RACE Hard and Soft Real-Time - Is there a compromise between hard real-time and best effort? - digital control and CM pipelines - Video Tape: RACE Platform 11/24 HOLIDAY - NO CLASS 12/01 REVIEW and Project Lab Work Final Quiz Review: Lecture Final-Quiz-Review 12/08 FINAL QUIZ 12/10 PROJECT WRITE-UP due in my e-mail inbox before mid-night and/or EE dept. box no later than 5:00 PM!!! (No late projects) 12/02 - 12/16 - Project Debug or Demo Sessions (Scheduled by e-mail with Instructor) 12/20 - Grades Finalized